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authorMatt Strapp <msattr@gmail.com>2020-02-28 11:20:34 -0600
committerMatt Strapp <msattr@gmail.com>2020-02-28 11:20:34 -0600
commit9416d720e118e4b5508ad17d64af0c9b69ff3a2f (patch)
tree8377222e117bcf97829713cce37c6525a2e50222 /Lab3.X/lab3_main_c.c
parentMerge origin/master (diff)
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Redo numpad
Diffstat (limited to '')
-rw-r--r--Lab3.X/lab3_main_c.c24
1 files changed, 12 insertions, 12 deletions
diff --git a/Lab3.X/lab3_main_c.c b/Lab3.X/lab3_main_c.c
index f917f4c..bf99269 100644
--- a/Lab3.X/lab3_main_c.c
+++ b/Lab3.X/lab3_main_c.c
@@ -14,23 +14,23 @@
#pragma config IOL1WAY = OFF // IOLOCK Protection (IOLOCK may be changed via unlocking seq)
#pragma config OSCIOFNC = ON // Primary Oscillator I/O Function (CLKO/RC15 functions as I/O pin)
#pragma config FCKSM = CSECME // Clock Switching and Monitor (Clock switching is enabled,
- // Fail-Safe Clock Monitor is enabled)
+// Fail-Safe Clock Monitor is enabled)
#pragma config FNOSC = FRCPLL // Oscillator Select (Fast RC Oscillator with PLL module (FRCPLL))
void delay(long n) {
- for (n=n; n>0; n--) {
- asm("nop");
- }
+ for (n = n; n > 0; n--) {
+ asm("nop");
+ }
}
void setup(void) {
- CLKDIVbits.RCDIV = 0; //Set RCDIV=1:1 (default 2:1) 32MHz or FCY/2=16M
- AD1PCFG = 0x9fff; //sets all pins to digital I/O
-// T1CON = 0;
-// PR1 = 15999;
-// TMR1 = 0;
-// IFS0bits.T1IF = 0;
-// T1CONbits.TON = 1;
+ CLKDIVbits.RCDIV = 0; //Set RCDIV=1:1 (default 2:1) 32MHz or FCY/2=16M
+ AD1PCFG = 0x9fff; //sets all pins to digital I/O
+ // T1CON = 0;
+ // PR1 = 15999;
+ // TMR1 = 0;
+ // IFS0bits.T1IF = 0;
+ // T1CONbits.TON = 1;
init7seg();
initKeyPad();
}
@@ -49,7 +49,7 @@ int main(void) {
right = temp;
}
showChar7seg(right, MSB);
- delay(200);
+ delay(200);
showChar7seg(left, LSB);
delay(200);
debounce++;