From 98850dad7260f2dc33e5726222be4decdf098e18 Mon Sep 17 00:00:00 2001
From: RossTheRoss <msattr@gmail.com>
Date: Sun, 23 Feb 2020 19:38:25 -0600
Subject: I hate this (Lab 3 partially working again)

---
 Lab3.X/lab3_main_c.c | 19 +++++++++++++++----
 1 file changed, 15 insertions(+), 4 deletions(-)

(limited to 'Lab3.X/lab3_main_c.c')

diff --git a/Lab3.X/lab3_main_c.c b/Lab3.X/lab3_main_c.c
index 1ead16d..406f657 100644
--- a/Lab3.X/lab3_main_c.c
+++ b/Lab3.X/lab3_main_c.c
@@ -17,6 +17,11 @@
                                        // Fail-Safe Clock Monitor is enabled)
 #pragma config FNOSC = FRCPLL      // Oscillator Select (Fast RC Oscillator with PLL module (FRCPLL))
 
+void delay(long n) {
+    for (n=n; n>0; n--) {
+            asm("nop");
+        }
+}
 
 void setup(void) {
     CLKDIVbits.RCDIV = 0;  //Set RCDIV=1:1 (default 2:1) 32MHz or FCY/2=16M
@@ -27,11 +32,17 @@ void setup(void) {
 
 int main(void) {
     setup();
+    char right, left, temp;
     while (1) {
-        showChar7seg('1', LSB);
-        delay(170);        
-        showChar7seg('0', MSB);
-        delay(170);
+        temp = readKeyPadRAW();
+        if (temp != '\0') {
+            left = right;
+            right = temp;
+        }
+        showChar7seg(right, LSB);
+        delay(200);        
+        showChar7seg(left, MSB);
+        delay(200);
     }
 }
 
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