do machine problem

1 files changed, 7 insertions, 4 deletions

diff --git a/ee4363/mp1/mipspipe.v b/ee4363/mp1/mp12/mipspipe.v
index 951bde0..62b4e8b 100644
--- a/ee4363/mp1/mipspipe.v
+++ b/ee4363/mp1/mp12/mipspipe.v
@@ -40,10 +40,12 @@ module mipspipe(clock);
       MEMWBIR = nop; // no-ops placed in pipeline latches
       // test some instructions
       for (i=0;i<=31;i=i+1) Regs[i] = i; // initialize registers
-      IMemory[0] = 32'h8c210003;
-      IMemory[1] = 32'hac020000;
-      IMemory[2] = 32'h00642820;
-      for (j=3;j<=1023;j=j+1) IMemory[j] = nop;
+IMemory[0] = 32'h00412820; // ADD OPCODE: 000000 00010 00001 00101 00000 100000
+      IMemory[1] = 32'h8CA30004; // First LW:   100011 00101 00011 00000 00000 00 0100
+      IMemory[2] = 32'h8C420000; // Second LW:  100011 00010 00010 00000 00000 000000
+      IMemory[3] = 32'h00A31825; // OR OPCODE:  000000 00101 00011 00011 00000 100101
+      IMemory[4] = 32'hACA30000; // SW:         101011 00101 00011 00000 00000 000000
+      for (j=5;j<=1023;j=j+1) IMemory[j] = nop;
       DMemory[0] = 32'h00000000;
       DMemory[1] = 32'hffffffff;
       for (k=2;k<=1023;k=k+1) DMemory[k] = 0;
@@ -67,6 +69,7 @@ module mipspipe(clock);
       else if (IDEXop==ALUop) begin // ALU operation
          case (IDEXIR[5:0]) // R-type instruction
            32: EXMEMALUOut <= Ain + Bin; // add operation
+           37: EXMEMALUOut <= Ain | Bin; //or
            default: ; // other R-type operations [to be implemented]
          endcase
       end