aboutsummaryrefslogtreecommitdiffstats
path: root/ee4363/mp1/mp12/test_mipspipe.vcd
diff options
context:
space:
mode:
Diffstat (limited to 'ee4363/mp1/mp12/test_mipspipe.vcd')
-rw-r--r--ee4363/mp1/mp12/test_mipspipe.vcd267
1 files changed, 267 insertions, 0 deletions
diff --git a/ee4363/mp1/mp12/test_mipspipe.vcd b/ee4363/mp1/mp12/test_mipspipe.vcd
new file mode 100644
index 0000000..2cda5d0
--- /dev/null
+++ b/ee4363/mp1/mp12/test_mipspipe.vcd
@@ -0,0 +1,267 @@
+$date
+ Thu Dec 3 09:49:50 2020
+$end
+$version
+ Icarus Verilog
+$end
+$timescale
+ 1s
+$end
+$scope module test_mipspipe $end
+$var reg 1 ! clock $end
+$var reg 4 " clock_cycle [3:0] $end
+$scope module u_mipspipe $end
+$var wire 32 # Ain [31:0] $end
+$var wire 32 $ Bin [31:0] $end
+$var wire 1 ! clock $end
+$var wire 5 % MEMWBrt [4:0] $end
+$var wire 5 & MEMWBrd [4:0] $end
+$var wire 6 ' MEMWBop [5:0] $end
+$var wire 5 ( IDEXrt [4:0] $end
+$var wire 5 ) IDEXrs [4:0] $end
+$var wire 6 * IDEXop [5:0] $end
+$var wire 5 + EXMEMrd [4:0] $end
+$var wire 6 , EXMEMop [5:0] $end
+$var reg 32 - EXMEMALUOut [31:0] $end
+$var reg 32 . EXMEMB [31:0] $end
+$var reg 32 / EXMEMIR [31:0] $end
+$var reg 32 0 IDEXA [31:0] $end
+$var reg 32 1 IDEXB [31:0] $end
+$var reg 32 2 IDEXIR [31:0] $end
+$var reg 32 3 IFIDIR [31:0] $end
+$var reg 32 4 MEMWBIR [31:0] $end
+$var reg 32 5 MEMWBValue [31:0] $end
+$var reg 32 6 PC [31:0] $end
+$var reg 6 7 i [5:0] $end
+$var reg 11 8 j [10:0] $end
+$var reg 11 9 k [10:0] $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+b10000000000 9
+b10000000000 8
+b100000 7
+b0 6
+bx 5
+b100000 4
+b100000 3
+b100000 2
+bx 1
+bx 0
+b100000 /
+bx .
+bx -
+b0 ,
+b0 +
+b0 *
+b0 )
+b0 (
+b0 '
+b0 &
+b0 %
+bx $
+bx #
+b0 "
+0!
+$end
+#5
+b0 $
+b0 1
+b0 #
+b0 0
+b100 6
+b10000010010100000100000 3
+b1 "
+1!
+#10
+0!
+#15
+b10 )
+b1 (
+b0 .
+b0 -
+b10000010010100000100000 2
+b1 $
+b1 1
+b10 #
+b10 0
+b1000 6
+b10001100101000110000000000000100 3
+b10 "
+1!
+#20
+0!
+#25
+b101 +
+b101 )
+b11 (
+b100011 *
+b0 5
+b1 .
+b10000010010100000100000 /
+b11 -
+b10001100101000110000000000000100 2
+b11 $
+b11 1
+b101 #
+b101 0
+b1100 6
+b10001100010000100000000000000000 3
+b11 "
+1!
+#30
+0!
+#35
+b101 &
+b1 %
+b0 +
+b100011 ,
+b10 )
+b10 (
+b10000010010100000100000 4
+b11 5
+b11 .
+b10001100101000110000000000000100 /
+b1001 -
+b10001100010000100000000000000000 2
+b10 $
+b10 1
+b10 #
+b10 0
+b10000 6
+b101000110001100000100101 3
+b100 "
+1!
+#40
+0!
+#45
+b0 &
+b11 %
+b100011 '
+b101 )
+b11 (
+b0 *
+b10001100101000110000000000000100 4
+b0 5
+b10 .
+b10001100010000100000000000000000 /
+b10 -
+b101000110001100000100101 2
+b11 $
+b11 1
+b101 #
+b101 0
+b10100 6
+b10101100101000110000000000000000 3
+b101 "
+1!
+#50
+0!
+#55
+b10 %
+b11 +
+b0 ,
+b101011 *
+b10001100010000100000000000000000 4
+b11 .
+b101000110001100000100101 /
+b111 -
+b10101100101000110000000000000000 2
+b11 #
+b11 0
+b11000 6
+b100000 3
+b110 "
+1!
+#60
+0!
+#65
+b11 &
+b11 %
+b0 '
+b0 +
+b101011 ,
+b0 )
+b0 (
+b0 *
+b101000110001100000100101 4
+b111 5
+b10101100101000110000000000000000 /
+b11 -
+b100000 2
+b0 $
+b0 1
+b0 #
+b0 0
+b11100 6
+b111 "
+1!
+#70
+0!
+#75
+b0 &
+b101011 '
+b0 ,
+b10101100101000110000000000000000 4
+b0 .
+b100000 /
+b0 -
+b100000 6
+b1000 "
+1!
+#80
+0!
+#85
+b0 %
+b0 '
+b100000 4
+b0 5
+b100100 6
+b1001 "
+1!
+#90
+0!
+#95
+b101000 6
+b1010 "
+1!
+#100
+0!
+#105
+b101100 6
+b1011 "
+1!
+#110
+0!
+#115
+b110000 6
+b1100 "
+1!
+#120
+0!
+#125
+b110100 6
+b1101 "
+1!
+#130
+0!
+#135
+b111000 6
+b1110 "
+1!
+#140
+0!
+#145
+b111100 6
+b1111 "
+1!
+#150
+0!
+#155
+b1000000 6
+b0 "
+1!
+#160
+0!