1 files changed, 413 insertions, 0 deletions
diff --git a/ee4363/mp2/test_mipspipe.vcd b/ee4363/mp2/test_mipspipe.vcd
new file mode 100644
index 0000000..3e076d6
--- /dev/null
+++ b/ee4363/mp2/test_mipspipe.vcd
@@ -0,0 +1,413 @@
+$date
+	Fri Dec 18 19:19:39 2020
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module test_mipspipe $end
+$var reg 1 ! clock $end
+$var reg 4 " clock_cycle [3:0] $end
+$scope module u_mipspipe_mp2 $end
+$var wire 32 # Bin [31:0] $end
+$var wire 1 $ STALL $end
+$var wire 1 % bypassAfromALUinWB $end
+$var wire 1 & bypassAfromLWinWB $end
+$var wire 1 ' bypassAfromMEM $end
+$var wire 1 ( bypassBfromALUinWB $end
+$var wire 1 ) bypassBfromLWinWB $end
+$var wire 1 * bypassBfromMEM $end
+$var wire 1 + bypassIDEXAfromWB $end
+$var wire 1 , bypassIDEXBfromWB $end
+$var wire 1 ! clock $end
+$var wire 5 - MEMWBrt [4:0] $end
+$var wire 5 . MEMWBrd [4:0] $end
+$var wire 6 / MEMWBop [5:0] $end
+$var wire 5 0 IFIDrt [4:0] $end
+$var wire 5 1 IFIDrs [4:0] $end
+$var wire 6 2 IFIDop [5:0] $end
+$var wire 5 3 IDEXrt [4:0] $end
+$var wire 5 4 IDEXrs [4:0] $end
+$var wire 6 5 IDEXop [5:0] $end
+$var wire 5 6 EXMEMrd [4:0] $end
+$var wire 6 7 EXMEMop [5:0] $end
+$var wire 32 8 Ain [31:0] $end
+$var reg 32 9 EXMEMALUOut [31:0] $end
+$var reg 32 : EXMEMB [31:0] $end
+$var reg 32 ; EXMEMIR [31:0] $end
+$var reg 32 < IDEXA [31:0] $end
+$var reg 32 = IDEXB [31:0] $end
+$var reg 32 > IDEXIR [31:0] $end
+$var reg 32 ? IFIDIR [31:0] $end
+$var reg 32 @ MEMWBIR [31:0] $end
+$var reg 32 A MEMWBValue [31:0] $end
+$var reg 32 B PC [31:0] $end
+$var reg 6 C i [5:0] $end
+$var reg 11 D j [10:0] $end
+$var reg 11 E k [10:0] $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
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+b10000000000 D
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+bx =
+bx <
+b100000 ;
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+0*
+0)
+0(
+0'
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+0%
+0$
+bx #
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+0!
+$end
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