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-rw-r--r--ee4363/mp1/mp12/mipspipe.v20
-rw-r--r--ee4363/mp1/mp12/out356
-rw-r--r--ee4363/mp1/mp12/test_mipspipe.vcd188
3 files changed, 324 insertions, 240 deletions
diff --git a/ee4363/mp1/mp12/mipspipe.v b/ee4363/mp1/mp12/mipspipe.v
index 62b4e8b..41d244d 100644
--- a/ee4363/mp1/mp12/mipspipe.v
+++ b/ee4363/mp1/mp12/mipspipe.v
@@ -40,12 +40,20 @@ module mipspipe(clock);
MEMWBIR = nop; // no-ops placed in pipeline latches
// test some instructions
for (i=0;i<=31;i=i+1) Regs[i] = i; // initialize registers
-IMemory[0] = 32'h00412820; // ADD OPCODE: 000000 00010 00001 00101 00000 100000
- IMemory[1] = 32'h8CA30004; // First LW: 100011 00101 00011 00000 00000 00 0100
- IMemory[2] = 32'h8C420000; // Second LW: 100011 00010 00010 00000 00000 000000
- IMemory[3] = 32'h00A31825; // OR OPCODE: 000000 00101 00011 00011 00000 100101
- IMemory[4] = 32'hACA30000; // SW: 101011 00101 00011 00000 00000 000000
- for (j=5;j<=1023;j=j+1) IMemory[j] = nop;
+ IMemory[0] = 32'h00412820; // ADD OPCODE: 000000 00010 00001 00101 00000 100000
+ IMemory[1] = nop;
+ IMemory[2] = nop;
+ IMemory[3] = nop;
+ IMemory[4] = 32'h8CA30004; // First LW: 100011 00101 00011 00000 00000 000100
+ IMemory[5] = 32'h8C420000; // Second LW: 100011 00010 00010 00000 00000 000000
+ IMemory[6] = nop;
+ IMemory[7] = nop;
+ IMemory[8] = 32'h00A31825; // OR OPCODE: 000000 00101 00011 00011 00000 100101
+ IMemory[9] = nop;
+ IMemory[10] =nop;
+ IMemory[11] = nop;
+ IMemory[12] = 32'hACA30000; // SW: 101011 00101 00011 00000 00000 000000
+ for (j=13;j<=1023;j=j+1) IMemory[j] = nop;
DMemory[0] = 32'h00000000;
DMemory[1] = 32'hffffffff;
for (k=2;k<=1023;k=k+1) DMemory[k] = 0;
diff --git a/ee4363/mp1/mp12/out b/ee4363/mp1/mp12/out
index 91338a7..5a975c9 100644
--- a/ee4363/mp1/mp12/out
+++ b/ee4363/mp1/mp12/out
@@ -6,207 +6,239 @@
:vpi_module "vhdl_sys";
:vpi_module "v2005_math";
:vpi_module "va_math";
-S_0x55a34db03e40 .scope module, "test_mipspipe" "test_mipspipe" 2 8;
+S_0x55c7b7006e40 .scope module, "test_mipspipe" "test_mipspipe" 2 8;
.timescale 0 0;
-v0x55a34db449f0_0 .var "clock", 0 0;
-v0x55a34db44a90_0 .var "clock_cycle", 3 0;
-E_0x55a34db17f80 .event negedge, v0x55a34db44650_0;
-S_0x55a34db039a0 .scope module, "u_mipspipe" "mipspipe" 2 14, 3 3 0, S_0x55a34db03e40;
+v0x55c7b704a350_0 .var "clock", 0 0;
+v0x55c7b704a3f0_0 .var "clock_cycle", 3 0;
+E_0x55c7b701af80 .event negedge, v0x55c7b7049fb0_0;
+S_0x55c7b70069a0 .scope module, "u_mipspipe" "mipspipe" 2 14, 3 3 0, S_0x55c7b7006e40;
.timescale 0 0;
.port_info 0 /INPUT 1 "clock"
-P_0x55a34db042e0 .param/l "ALUop" 0 3 8, C4<000000>;
-P_0x55a34db04320 .param/l "BEQ" 0 3 8, C4<000100>;
-P_0x55a34db04360 .param/l "LW" 0 3 8, C4<100011>;
-P_0x55a34db043a0 .param/l "SW" 0 3 8, C4<101011>;
-P_0x55a34db043e0 .param/l "nop" 0 3 8, C4<00000000000000000000000000100000>;
-L_0x55a34dadea40 .functor BUFZ 32, v0x55a34db43970_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
-L_0x55a34dade820 .functor BUFZ 32, v0x55a34db43a50_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
-v0x55a34db0c970_0 .net "Ain", 31 0, L_0x55a34dadea40; 1 drivers
-v0x55a34db43340_0 .net "Bin", 31 0, L_0x55a34dade820; 1 drivers
-v0x55a34db43420 .array "DMemory", 1023 0, 31 0;
-v0x55a34db434c0_0 .var "EXMEMALUOut", 31 0;
-v0x55a34db435a0_0 .var "EXMEMB", 31 0;
-v0x55a34db436d0_0 .var "EXMEMIR", 31 0;
-v0x55a34db437b0_0 .net "EXMEMop", 5 0, L_0x55a34db44fb0; 1 drivers
-v0x55a34db43890_0 .net "EXMEMrd", 4 0, L_0x55a34db44c90; 1 drivers
-v0x55a34db43970_0 .var "IDEXA", 31 0;
-v0x55a34db43a50_0 .var "IDEXB", 31 0;
-v0x55a34db43b30_0 .var "IDEXIR", 31 0;
-v0x55a34db43c10_0 .net "IDEXop", 5 0, L_0x55a34db45180; 1 drivers
-v0x55a34db43cf0_0 .net "IDEXrs", 4 0, L_0x55a34db44b50; 1 drivers
-v0x55a34db43dd0_0 .net "IDEXrt", 4 0, L_0x55a34db44bf0; 1 drivers
-v0x55a34db43eb0_0 .var "IFIDIR", 31 0;
-v0x55a34db43f90 .array "IMemory", 1023 0, 31 0;
-v0x55a34db44050_0 .var "MEMWBIR", 31 0;
-v0x55a34db44130_0 .var "MEMWBValue", 31 0;
-v0x55a34db44210_0 .net "MEMWBop", 5 0, L_0x55a34db450e0; 1 drivers
-v0x55a34db442f0_0 .net "MEMWBrd", 4 0, L_0x55a34db44d60; 1 drivers
-v0x55a34db443d0_0 .net "MEMWBrt", 4 0, L_0x55a34db44e90; 1 drivers
-v0x55a34db444b0_0 .var "PC", 31 0;
-v0x55a34db44590 .array "Regs", 31 0, 31 0;
-v0x55a34db44650_0 .net "clock", 0 0, v0x55a34db449f0_0; 1 drivers
-v0x55a34db44710_0 .var "i", 5 0;
-v0x55a34db447f0_0 .var "j", 10 0;
-v0x55a34db448d0_0 .var "k", 10 0;
-E_0x55a34db18270 .event posedge, v0x55a34db44650_0;
-L_0x55a34db44b50 .part v0x55a34db43b30_0, 21, 5;
-L_0x55a34db44bf0 .part v0x55a34db43b30_0, 16, 5;
-L_0x55a34db44c90 .part v0x55a34db436d0_0, 11, 5;
-L_0x55a34db44d60 .part v0x55a34db44050_0, 11, 5;
-L_0x55a34db44e90 .part v0x55a34db44050_0, 16, 5;
-L_0x55a34db44fb0 .part v0x55a34db436d0_0, 26, 6;
-L_0x55a34db450e0 .part v0x55a34db44050_0, 26, 6;
-L_0x55a34db45180 .part v0x55a34db43b30_0, 26, 6;
- .scope S_0x55a34db039a0;
+P_0x55c7b70072e0 .param/l "ALUop" 0 3 8, C4<000000>;
+P_0x55c7b7007320 .param/l "BEQ" 0 3 8, C4<000100>;
+P_0x55c7b7007360 .param/l "LW" 0 3 8, C4<100011>;
+P_0x55c7b70073a0 .param/l "SW" 0 3 8, C4<101011>;
+P_0x55c7b70073e0 .param/l "nop" 0 3 8, C4<00000000000000000000000000100000>;
+L_0x55c7b6fe1a40 .functor BUFZ 32, v0x55c7b70492d0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+L_0x55c7b6fe1820 .functor BUFZ 32, v0x55c7b70493b0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+v0x55c7b7010de0_0 .net "Ain", 31 0, L_0x55c7b6fe1a40; 1 drivers
+v0x55c7b7048ca0_0 .net "Bin", 31 0, L_0x55c7b6fe1820; 1 drivers
+v0x55c7b7048d80 .array "DMemory", 1023 0, 31 0;
+v0x55c7b7048e20_0 .var "EXMEMALUOut", 31 0;
+v0x55c7b7048f00_0 .var "EXMEMB", 31 0;
+v0x55c7b7049030_0 .var "EXMEMIR", 31 0;
+v0x55c7b7049110_0 .net "EXMEMop", 5 0, L_0x55c7b704a910; 1 drivers
+v0x55c7b70491f0_0 .net "EXMEMrd", 4 0, L_0x55c7b704a5f0; 1 drivers
+v0x55c7b70492d0_0 .var "IDEXA", 31 0;
+v0x55c7b70493b0_0 .var "IDEXB", 31 0;
+v0x55c7b7049490_0 .var "IDEXIR", 31 0;
+v0x55c7b7049570_0 .net "IDEXop", 5 0, L_0x55c7b704aae0; 1 drivers
+v0x55c7b7049650_0 .net "IDEXrs", 4 0, L_0x55c7b704a4b0; 1 drivers
+v0x55c7b7049730_0 .net "IDEXrt", 4 0, L_0x55c7b704a550; 1 drivers
+v0x55c7b7049810_0 .var "IFIDIR", 31 0;
+v0x55c7b70498f0 .array "IMemory", 1023 0, 31 0;
+v0x55c7b70499b0_0 .var "MEMWBIR", 31 0;
+v0x55c7b7049a90_0 .var "MEMWBValue", 31 0;
+v0x55c7b7049b70_0 .net "MEMWBop", 5 0, L_0x55c7b704aa40; 1 drivers
+v0x55c7b7049c50_0 .net "MEMWBrd", 4 0, L_0x55c7b704a6c0; 1 drivers
+v0x55c7b7049d30_0 .net "MEMWBrt", 4 0, L_0x55c7b704a7f0; 1 drivers
+v0x55c7b7049e10_0 .var "PC", 31 0;
+v0x55c7b7049ef0 .array "Regs", 31 0, 31 0;
+v0x55c7b7049fb0_0 .net "clock", 0 0, v0x55c7b704a350_0; 1 drivers
+v0x55c7b704a070_0 .var "i", 5 0;
+v0x55c7b704a150_0 .var "j", 10 0;
+v0x55c7b704a230_0 .var "k", 10 0;
+E_0x55c7b701b270 .event posedge, v0x55c7b7049fb0_0;
+L_0x55c7b704a4b0 .part v0x55c7b7049490_0, 21, 5;
+L_0x55c7b704a550 .part v0x55c7b7049490_0, 16, 5;
+L_0x55c7b704a5f0 .part v0x55c7b7049030_0, 11, 5;
+L_0x55c7b704a6c0 .part v0x55c7b70499b0_0, 11, 5;
+L_0x55c7b704a7f0 .part v0x55c7b70499b0_0, 16, 5;
+L_0x55c7b704a910 .part v0x55c7b7049030_0, 26, 6;
+L_0x55c7b704aa40 .part v0x55c7b70499b0_0, 26, 6;
+L_0x55c7b704aae0 .part v0x55c7b7049490_0, 26, 6;
+ .scope S_0x55c7b70069a0;
T_0 ;
%pushi/vec4 0, 0, 32;
- %store/vec4 v0x55a34db444b0_0, 0, 32;
+ %store/vec4 v0x55c7b7049e10_0, 0, 32;
%pushi/vec4 32, 0, 32;
- %store/vec4 v0x55a34db43eb0_0, 0, 32;
+ %store/vec4 v0x55c7b7049810_0, 0, 32;
%pushi/vec4 32, 0, 32;
- %store/vec4 v0x55a34db43b30_0, 0, 32;
+ %store/vec4 v0x55c7b7049490_0, 0, 32;
%pushi/vec4 32, 0, 32;
- %store/vec4 v0x55a34db436d0_0, 0, 32;
+ %store/vec4 v0x55c7b7049030_0, 0, 32;
%pushi/vec4 32, 0, 32;
- %store/vec4 v0x55a34db44050_0, 0, 32;
+ %store/vec4 v0x55c7b70499b0_0, 0, 32;
%pushi/vec4 0, 0, 6;
- %store/vec4 v0x55a34db44710_0, 0, 6;
+ %store/vec4 v0x55c7b704a070_0, 0, 6;
T_0.0 ;
- %load/vec4 v0x55a34db44710_0;
+ %load/vec4 v0x55c7b704a070_0;
%pad/u 32;
%cmpi/u 31, 0, 32;
%flag_or 5, 4;
%jmp/0xz T_0.1, 5;
- %load/vec4 v0x55a34db44710_0;
+ %load/vec4 v0x55c7b704a070_0;
%pad/u 32;
- %load/vec4 v0x55a34db44710_0;
+ %load/vec4 v0x55c7b704a070_0;
%pad/u 7;
%ix/vec4 4;
- %store/vec4a v0x55a34db44590, 4, 0;
- %load/vec4 v0x55a34db44710_0;
+ %store/vec4a v0x55c7b7049ef0, 4, 0;
+ %load/vec4 v0x55c7b704a070_0;
%addi 1, 0, 6;
- %store/vec4 v0x55a34db44710_0, 0, 6;
+ %store/vec4 v0x55c7b704a070_0, 0, 6;
%jmp T_0.0;
T_0.1 ;
%pushi/vec4 4270112, 0, 32;
%ix/load 4, 0, 0;
%flag_set/imm 4, 0;
- %store/vec4a v0x55a34db43f90, 4, 0;
- %pushi/vec4 2359492612, 0, 32;
+ %store/vec4a v0x55c7b70498f0, 4, 0;
+ %pushi/vec4 32, 0, 32;
%ix/load 4, 1, 0;
%flag_set/imm 4, 0;
- %store/vec4a v0x55a34db43f90, 4, 0;
- %pushi/vec4 2353135616, 0, 32;
+ %store/vec4a v0x55c7b70498f0, 4, 0;
+ %pushi/vec4 32, 0, 32;
%ix/load 4, 2, 0;
%flag_set/imm 4, 0;
- %store/vec4a v0x55a34db43f90, 4, 0;
- %pushi/vec4 10688549, 0, 32;
+ %store/vec4a v0x55c7b70498f0, 4, 0;
+ %pushi/vec4 32, 0, 32;
%ix/load 4, 3, 0;
%flag_set/imm 4, 0;
- %store/vec4a v0x55a34db43f90, 4, 0;
- %pushi/vec4 2896363520, 0, 32;
+ %store/vec4a v0x55c7b70498f0, 4, 0;
+ %pushi/vec4 2359492612, 0, 32;
%ix/load 4, 4, 0;
%flag_set/imm 4, 0;
- %store/vec4a v0x55a34db43f90, 4, 0;
- %pushi/vec4 5, 0, 11;
- %store/vec4 v0x55a34db447f0_0, 0, 11;
+ %store/vec4a v0x55c7b70498f0, 4, 0;
+ %pushi/vec4 2353135616, 0, 32;
+ %ix/load 4, 5, 0;
+ %flag_set/imm 4, 0;
+ %store/vec4a v0x55c7b70498f0, 4, 0;
+ %pushi/vec4 32, 0, 32;
+ %ix/load 4, 6, 0;
+ %flag_set/imm 4, 0;
+ %store/vec4a v0x55c7b70498f0, 4, 0;
+ %pushi/vec4 32, 0, 32;
+ %ix/load 4, 7, 0;
+ %flag_set/imm 4, 0;
+ %store/vec4a v0x55c7b70498f0, 4, 0;
+ %pushi/vec4 10688549, 0, 32;
+ %ix/load 4, 8, 0;
+ %flag_set/imm 4, 0;
+ %store/vec4a v0x55c7b70498f0, 4, 0;
+ %pushi/vec4 32, 0, 32;
+ %ix/load 4, 9, 0;
+ %flag_set/imm 4, 0;
+ %store/vec4a v0x55c7b70498f0, 4, 0;
+ %pushi/vec4 32, 0, 32;
+ %ix/load 4, 10, 0;
+ %flag_set/imm 4, 0;
+ %store/vec4a v0x55c7b70498f0, 4, 0;
+ %pushi/vec4 32, 0, 32;
+ %ix/load 4, 11, 0;
+ %flag_set/imm 4, 0;
+ %store/vec4a v0x55c7b70498f0, 4, 0;
+ %pushi/vec4 2896363520, 0, 32;
+ %ix/load 4, 12, 0;
+ %flag_set/imm 4, 0;
+ %store/vec4a v0x55c7b70498f0, 4, 0;
+ %pushi/vec4 13, 0, 11;
+ %store/vec4 v0x55c7b704a150_0, 0, 11;
T_0.2 ;
- %load/vec4 v0x55a34db447f0_0;
+ %load/vec4 v0x55c7b704a150_0;
%pad/u 32;
%cmpi/u 1023, 0, 32;
%flag_or 5, 4;
%jmp/0xz T_0.3, 5;
%pushi/vec4 32, 0, 32;
- %load/vec4 v0x55a34db447f0_0;
+ %load/vec4 v0x55c7b704a150_0;
%pad/u 12;
%ix/vec4 4;
- %store/vec4a v0x55a34db43f90, 4, 0;
- %load/vec4 v0x55a34db447f0_0;
+ %store/vec4a v0x55c7b70498f0, 4, 0;
+ %load/vec4 v0x55c7b704a150_0;
%addi 1, 0, 11;
- %store/vec4 v0x55a34db447f0_0, 0, 11;
+ %store/vec4 v0x55c7b704a150_0, 0, 11;
%jmp T_0.2;
T_0.3 ;
%pushi/vec4 0, 0, 32;
%ix/load 4, 0, 0;
%flag_set/imm 4, 0;
- %store/vec4a v0x55a34db43420, 4, 0;
+ %store/vec4a v0x55c7b7048d80, 4, 0;
%pushi/vec4 4294967295, 0, 32;
%ix/load 4, 1, 0;
%flag_set/imm 4, 0;
- %store/vec4a v0x55a34db43420, 4, 0;
+ %store/vec4a v0x55c7b7048d80, 4, 0;
%pushi/vec4 2, 0, 11;
- %store/vec4 v0x55a34db448d0_0, 0, 11;
+ %store/vec4 v0x55c7b704a230_0, 0, 11;
T_0.4 ;
- %load/vec4 v0x55a34db448d0_0;
+ %load/vec4 v0x55c7b704a230_0;
%pad/u 32;
%cmpi/u 1023, 0, 32;
%flag_or 5, 4;
%jmp/0xz T_0.5, 5;
%pushi/vec4 0, 0, 32;
- %load/vec4 v0x55a34db448d0_0;
+ %load/vec4 v0x55c7b704a230_0;
%pad/u 12;
%ix/vec4 4;
- %store/vec4a v0x55a34db43420, 4, 0;
- %load/vec4 v0x55a34db448d0_0;
+ %store/vec4a v0x55c7b7048d80, 4, 0;
+ %load/vec4 v0x55c7b704a230_0;
%addi 1, 0, 11;
- %store/vec4 v0x55a34db448d0_0, 0, 11;
+ %store/vec4 v0x55c7b704a230_0, 0, 11;
%jmp T_0.4;
T_0.5 ;
%end;
.thread T_0;
- .scope S_0x55a34db039a0;
+ .scope S_0x55c7b70069a0;
T_1 ;
- %wait E_0x55a34db18270;
- %load/vec4 v0x55a34db444b0_0;
+ %wait E_0x55c7b701b270;
+ %load/vec4 v0x55c7b7049e10_0;
%ix/load 5, 2, 0;
%flag_set/imm 4, 0;
%shiftr 5;
%ix/vec4 4;
- %load/vec4a v0x55a34db43f90, 4;
- %assign/vec4 v0x55a34db43eb0_0, 0;
- %load/vec4 v0x55a34db444b0_0;
+ %load/vec4a v0x55c7b70498f0, 4;
+ %assign/vec4 v0x55c7b7049810_0, 0;
+ %load/vec4 v0x55c7b7049e10_0;
%addi 4, 0, 32;
- %assign/vec4 v0x55a34db444b0_0, 0;
- %load/vec4 v0x55a34db43eb0_0;
+ %assign/vec4 v0x55c7b7049e10_0, 0;
+ %load/vec4 v0x55c7b7049810_0;
%parti/s 5, 21, 6;
%pad/u 7;
%ix/vec4 4;
- %load/vec4a v0x55a34db44590, 4;
- %assign/vec4 v0x55a34db43970_0, 0;
- %load/vec4 v0x55a34db43eb0_0;
+ %load/vec4a v0x55c7b7049ef0, 4;
+ %assign/vec4 v0x55c7b70492d0_0, 0;
+ %load/vec4 v0x55c7b7049810_0;
%parti/s 5, 16, 6;
%pad/u 7;
%ix/vec4 4;
- %load/vec4a v0x55a34db44590, 4;
- %assign/vec4 v0x55a34db43a50_0, 0;
- %load/vec4 v0x55a34db43eb0_0;
- %assign/vec4 v0x55a34db43b30_0, 0;
- %load/vec4 v0x55a34db43c10_0;
+ %load/vec4a v0x55c7b7049ef0, 4;
+ %assign/vec4 v0x55c7b70493b0_0, 0;
+ %load/vec4 v0x55c7b7049810_0;
+ %assign/vec4 v0x55c7b7049490_0, 0;
+ %load/vec4 v0x55c7b7049570_0;
%pushi/vec4 35, 0, 6;
%cmp/e;
%flag_get/vec4 4;
- %load/vec4 v0x55a34db43c10_0;
+ %load/vec4 v0x55c7b7049570_0;
%pushi/vec4 43, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%flag_set/vec4 8;
%jmp/0xz T_1.0, 8;
- %load/vec4 v0x55a34db43970_0;
- %load/vec4 v0x55a34db43b30_0;
+ %load/vec4 v0x55c7b70492d0_0;
+ %load/vec4 v0x55c7b7049490_0;
%parti/s 1, 15, 5;
%replicate 16;
- %load/vec4 v0x55a34db43b30_0;
+ %load/vec4 v0x55c7b7049490_0;
%parti/s 16, 0, 2;
%concat/vec4; draw_concat_vec4
%add;
- %assign/vec4 v0x55a34db434c0_0, 0;
+ %assign/vec4 v0x55c7b7048e20_0, 0;
%jmp T_1.1;
T_1.0 ;
- %load/vec4 v0x55a34db43c10_0;
+ %load/vec4 v0x55c7b7049570_0;
%cmpi/e 0, 0, 6;
%jmp/0xz T_1.2, 4;
- %load/vec4 v0x55a34db43b30_0;
+ %load/vec4 v0x55c7b7049490_0;
%parti/s 6, 0, 2;
%dup/vec4;
%pushi/vec4 32, 0, 6;
@@ -218,65 +250,65 @@ T_1.0 ;
%jmp/1 T_1.5, 6;
%jmp T_1.7;
T_1.4 ;
- %load/vec4 v0x55a34db0c970_0;
- %load/vec4 v0x55a34db43340_0;
+ %load/vec4 v0x55c7b7010de0_0;
+ %load/vec4 v0x55c7b7048ca0_0;
%add;
- %assign/vec4 v0x55a34db434c0_0, 0;
+ %assign/vec4 v0x55c7b7048e20_0, 0;
%jmp T_1.7;
T_1.5 ;
- %load/vec4 v0x55a34db0c970_0;
- %load/vec4 v0x55a34db43340_0;
+ %load/vec4 v0x55c7b7010de0_0;
+ %load/vec4 v0x55c7b7048ca0_0;
%or;
- %assign/vec4 v0x55a34db434c0_0, 0;
+ %assign/vec4 v0x55c7b7048e20_0, 0;
%jmp T_1.7;
T_1.7 ;
%pop/vec4 1;
T_1.2 ;
T_1.1 ;
- %load/vec4 v0x55a34db43b30_0;
- %assign/vec4 v0x55a34db436d0_0, 0;
- %load/vec4 v0x55a34db43a50_0;
- %assign/vec4 v0x55a34db435a0_0, 0;
- %load/vec4 v0x55a34db437b0_0;
+ %load/vec4 v0x55c7b7049490_0;
+ %assign/vec4 v0x55c7b7049030_0, 0;
+ %load/vec4 v0x55c7b70493b0_0;
+ %assign/vec4 v0x55c7b7048f00_0, 0;
+ %load/vec4 v0x55c7b7049110_0;
%cmpi/e 0, 0, 6;
%jmp/0xz T_1.8, 4;
- %load/vec4 v0x55a34db434c0_0;
- %assign/vec4 v0x55a34db44130_0, 0;
+ %load/vec4 v0x55c7b7048e20_0;
+ %assign/vec4 v0x55c7b7049a90_0, 0;
%jmp T_1.9;
T_1.8 ;
- %load/vec4 v0x55a34db437b0_0;
+ %load/vec4 v0x55c7b7049110_0;
%cmpi/e 35, 0, 6;
%jmp/0xz T_1.10, 4;
- %load/vec4 v0x55a34db434c0_0;
+ %load/vec4 v0x55c7b7048e20_0;
%ix/load 5, 2, 0;
%flag_set/imm 4, 0;
%shiftr 5;
%ix/vec4 4;
- %load/vec4a v0x55a34db43420, 4;
- %assign/vec4 v0x55a34db44130_0, 0;
+ %load/vec4a v0x55c7b7048d80, 4;
+ %assign/vec4 v0x55c7b7049a90_0, 0;
%jmp T_1.11;
T_1.10 ;
- %load/vec4 v0x55a34db437b0_0;
+ %load/vec4 v0x55c7b7049110_0;
%cmpi/e 43, 0, 6;
%jmp/0xz T_1.12, 4;
- %load/vec4 v0x55a34db435a0_0;
- %load/vec4 v0x55a34db434c0_0;
+ %load/vec4 v0x55c7b7048f00_0;
+ %load/vec4 v0x55c7b7048e20_0;
%ix/load 4, 2, 0;
%flag_set/imm 4, 0;
%shiftr 4;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
- %assign/vec4/a/d v0x55a34db43420, 0, 4;
+ %assign/vec4/a/d v0x55c7b7048d80, 0, 4;
T_1.12 ;
T_1.11 ;
T_1.9 ;
- %load/vec4 v0x55a34db436d0_0;
- %assign/vec4 v0x55a34db44050_0, 0;
- %load/vec4 v0x55a34db44210_0;
+ %load/vec4 v0x55c7b7049030_0;
+ %assign/vec4 v0x55c7b70499b0_0, 0;
+ %load/vec4 v0x55c7b7049b70_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
- %load/vec4 v0x55a34db442f0_0;
+ %load/vec4 v0x55c7b7049c50_0;
%pad/u 32;
%pushi/vec4 0, 0, 32;
%cmp/e;
@@ -285,19 +317,19 @@ T_1.9 ;
%and;
%flag_set/vec4 8;
%jmp/0xz T_1.14, 8;
- %load/vec4 v0x55a34db44130_0;
- %load/vec4 v0x55a34db442f0_0;
+ %load/vec4 v0x55c7b7049a90_0;
+ %load/vec4 v0x55c7b7049c50_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
- %assign/vec4/a/d v0x55a34db44590, 0, 4;
+ %assign/vec4/a/d v0x55c7b7049ef0, 0, 4;
%jmp T_1.15;
T_1.14 ;
- %load/vec4 v0x55a34db44210_0;
+ %load/vec4 v0x55c7b7049b70_0;
%pushi/vec4 35, 0, 6;
%cmp/e;
%flag_get/vec4 4;
- %load/vec4 v0x55a34db443d0_0;
+ %load/vec4 v0x55c7b7049d30_0;
%pad/u 32;
%pushi/vec4 0, 0, 32;
%cmp/e;
@@ -306,56 +338,56 @@ T_1.14 ;
%and;
%flag_set/vec4 8;
%jmp/0xz T_1.16, 8;
- %load/vec4 v0x55a34db44130_0;
- %load/vec4 v0x55a34db443d0_0;
+ %load/vec4 v0x55c7b7049a90_0;
+ %load/vec4 v0x55c7b7049d30_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
- %assign/vec4/a/d v0x55a34db44590, 0, 4;
+ %assign/vec4/a/d v0x55c7b7049ef0, 0, 4;
T_1.16 ;
T_1.15 ;
%jmp T_1;
.thread T_1;
- .scope S_0x55a34db03e40;
+ .scope S_0x55c7b7006e40;
T_2 ;
%pushi/vec4 0, 0, 1;
- %store/vec4 v0x55a34db449f0_0, 0, 1;
+ %store/vec4 v0x55c7b704a350_0, 0, 1;
%pushi/vec4 0, 0, 4;
- %store/vec4 v0x55a34db44a90_0, 0, 4;
+ %store/vec4 v0x55c7b704a3f0_0, 0, 4;
%delay 160, 0;
%vpi_call 2 20 "$finish" {0 0 0};
%end;
.thread T_2;
- .scope S_0x55a34db03e40;
+ .scope S_0x55c7b7006e40;
T_3 ;
%delay 5, 0;
- %load/vec4 v0x55a34db449f0_0;
+ %load/vec4 v0x55c7b704a350_0;
%inv;
- %store/vec4 v0x55a34db449f0_0, 0, 1;
+ %store/vec4 v0x55c7b704a350_0, 0, 1;
%jmp T_3;
.thread T_3;
- .scope S_0x55a34db03e40;
+ .scope S_0x55c7b7006e40;
T_4 ;
- %wait E_0x55a34db18270;
- %load/vec4 v0x55a34db44a90_0;
+ %wait E_0x55c7b701b270;
+ %load/vec4 v0x55c7b704a3f0_0;
%addi 1, 0, 4;
- %store/vec4 v0x55a34db44a90_0, 0, 4;
+ %store/vec4 v0x55c7b704a3f0_0, 0, 4;
%jmp T_4;
.thread T_4;
- .scope S_0x55a34db03e40;
+ .scope S_0x55c7b7006e40;
T_5 ;
- %wait E_0x55a34db17f80;
- %vpi_call 2 36 "$display", "\012\012clock cycle = %d", v0x55a34db44a90_0, " (time = %1.0t)", $time {0 0 0};
- %vpi_call 2 37 "$display", "IF/ID registers\012\011 IF/ID.PC+4 = %h, IF/ID.IR = %h \012", v0x55a34db444b0_0, v0x55a34db43eb0_0 {0 0 0};
- %vpi_call 2 38 "$display", "ID/EX registers\012\011 ID/EX.rs = %d, ID/EX.rt = %d", v0x55a34db43cf0_0, v0x55a34db43dd0_0, "\012\011 ID/EX.A = %h, ID/EX.B = %h", v0x55a34db43970_0, v0x55a34db43a50_0 {0 0 0};
- %vpi_call 2 39 "$display", "\011 ID/EX.op = %h\012", v0x55a34db43c10_0 {0 0 0};
- %vpi_call 2 40 "$display", "EX/MEM registers\012\011 EX/MEM.rs = %d, EX/MEM.rt = %d", v0x55a34db43cf0_0, v0x55a34db43dd0_0, "\012\011 EX/MEM.ALUOut = %h, EX/MEM.ALUout = %h", v0x55a34db434c0_0, v0x55a34db435a0_0 {0 0 0};
- %vpi_call 2 41 "$display", "\011 EX/MEM.op = %h\012", v0x55a34db437b0_0 {0 0 0};
- %vpi_call 2 42 "$display", "MEM/WB registers\012\011 MEM/WB.rd = %d, MEM/WB.rt = %d", v0x55a34db442f0_0, v0x55a34db443d0_0, "\012\011 MEM/WB.value = %h", v0x55a34db44130_0 {0 0 0};
- %vpi_call 2 43 "$display", "\011 EX/MEM.op = %h\012", v0x55a34db44210_0 {0 0 0};
+ %wait E_0x55c7b701af80;
+ %vpi_call 2 36 "$display", "\012\012clock cycle = %d", v0x55c7b704a3f0_0, " (time = %1.0t)", $time {0 0 0};
+ %vpi_call 2 37 "$display", "IF/ID registers\012\011 IF/ID.PC+4 = %h, IF/ID.IR = %h \012", v0x55c7b7049e10_0, v0x55c7b7049810_0 {0 0 0};
+ %vpi_call 2 38 "$display", "ID/EX registers\012\011 ID/EX.rs = %d, ID/EX.rt = %d", v0x55c7b7049650_0, v0x55c7b7049730_0, "\012\011 ID/EX.A = %h, ID/EX.B = %h", v0x55c7b70492d0_0, v0x55c7b70493b0_0 {0 0 0};
+ %vpi_call 2 39 "$display", "\011 ID/EX.op = %h\012", v0x55c7b7049570_0 {0 0 0};
+ %vpi_call 2 40 "$display", "EX/MEM registers\012\011 EX/MEM.rs = %d, EX/MEM.rt = %d", v0x55c7b7049650_0, v0x55c7b7049730_0, "\012\011 EX/MEM.ALUOut = %h, EX/MEM.ALUout = %h", v0x55c7b7048e20_0, v0x55c7b7048f00_0 {0 0 0};
+ %vpi_call 2 41 "$display", "\011 EX/MEM.op = %h\012", v0x55c7b7049110_0 {0 0 0};
+ %vpi_call 2 42 "$display", "MEM/WB registers\012\011 MEM/WB.rd = %d, MEM/WB.rt = %d", v0x55c7b7049c50_0, v0x55c7b7049d30_0, "\012\011 MEM/WB.value = %h", v0x55c7b7049a90_0 {0 0 0};
+ %vpi_call 2 43 "$display", "\011 EX/MEM.op = %h\012", v0x55c7b7049b70_0 {0 0 0};
%jmp T_5;
.thread T_5;
- .scope S_0x55a34db03e40;
+ .scope S_0x55c7b7006e40;
T_6 ;
%vpi_call 2 49 "$dumpfile", "test_mipspipe.vcd" {0 0 0};
%vpi_call 2 50 "$dumpvars" {0 0 0};
diff --git a/ee4363/mp1/mp12/test_mipspipe.vcd b/ee4363/mp1/mp12/test_mipspipe.vcd
index 2cda5d0..9a6b26f 100644
--- a/ee4363/mp1/mp12/test_mipspipe.vcd
+++ b/ee4363/mp1/mp12/test_mipspipe.vcd
@@ -1,5 +1,5 @@
$date
- Thu Dec 3 09:49:50 2020
+ Thu Dec 3 12:05:26 2020
$end
$version
Icarus Verilog
@@ -88,27 +88,25 @@ b1 1
b10 #
b10 0
b1000 6
-b10001100101000110000000000000100 3
+b100000 3
b10 "
1!
#20
0!
#25
b101 +
-b101 )
-b11 (
-b100011 *
+b0 )
+b0 (
b0 5
b1 .
b10000010010100000100000 /
b11 -
-b10001100101000110000000000000100 2
-b11 $
-b11 1
-b101 #
-b101 0
+b100000 2
+b0 $
+b0 1
+b0 #
+b0 0
b1100 6
-b10001100010000100000000000000000 3
b11 "
1!
#30
@@ -117,149 +115,195 @@ b11 "
b101 &
b1 %
b0 +
-b100011 ,
-b10 )
-b10 (
b10000010010100000100000 4
b11 5
-b11 .
-b10001100101000110000000000000100 /
-b1001 -
-b10001100010000100000000000000000 2
-b10 $
-b10 1
-b10 #
-b10 0
+b0 .
+b100000 /
+b0 -
b10000 6
-b101000110001100000100101 3
b100 "
1!
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b0 &
-b11 %
-b100011 '
-b101 )
-b11 (
-b0 *
-b10001100101000110000000000000100 4
+b0 %
+b100000 4
b0 5
-b10 .
-b10001100010000100000000000000000 /
-b10 -
-b101000110001100000100101 2
-b11 $
-b11 1
-b101 #
-b101 0
b10100 6
-b10101100101000110000000000000000 3
+b10001100101000110000000000000100 3
b101 "
1!
#50
0!
#55
-b10 %
-b11 +
-b0 ,
-b101011 *
-b10001100010000100000000000000000 4
-b11 .
-b101000110001100000100101 /
-b111 -
-b10101100101000110000000000000000 2
+b101 )
+b11 (
+b100011 *
+b10001100101000110000000000000100 2
+b11 $
+b11 1
b11 #
b11 0
b11000 6
-b100000 3
+b10001100010000100000000000000000 3
b110 "
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+b100011 ,
+b10 )
+b10 (
+b11 .
+b10001100101000110000000000000100 /
+b111 -
+b10001100010000100000000000000000 2
+b10 $
+b10 1
+b10 #
+b10 0
+b11100 6
+b100000 3
+b111 "
+1!
+#70
+0!
+#75
b11 %
-b0 '
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+b100011 '
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-b101000110001100000100101 4
-b111 5
-b10101100101000110000000000000000 /
-b11 -
+b10001100101000110000000000000100 4
+b11111111111111111111111111111111 5
+b10 .
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+b10 -
b100000 2
b0 $
b0 1
b0 #
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-b11100 6
-b111 "
-1!
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+b10 %
+b0 ,
+b10001100010000100000000000000000 4
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+b101000110001100000100101 3
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+b0 %
+b0 '
+b101 )
+b11 (
+b100000 4
+b101000110001100000100101 2
+b11111111111111111111111111111111 $
+b11111111111111111111111111111111 1
+b11 #
+b11 0
b101000 6
+b100000 3
b1010 "
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+b11 +
+b0 )
+b0 (
+b11111111111111111111111111111111 .
+b101000110001100000100101 /
+b11111111111111111111111111111111 -
+b100000 2
+b0 $
+b0 1
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+b101 )
+b11 (
+b101011 *
+b10101100101000110000000000000000 2
+b11111111111111111111111111111111 $
+b11111111111111111111111111111111 1
+b11 #
+b11 0
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+b10101100101000110000000000000000 /
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