From 8486478a788896848fd1d90448d41bb5ebbbe059 Mon Sep 17 00:00:00 2001 From: RossTheRoss Date: Thu, 3 Dec 2020 09:50:18 -0600 Subject: do machine problem --- ee4363/mp1/MIPSALU.v | 18 -- ee4363/mp1/MIPSAlu.vcd | 57 ------ ee4363/mp1/mipspipe.v | 90 ---------- ee4363/mp1/mp11/MIPSALU.v | 18 ++ ee4363/mp1/mp11/MIPSAlu.vcd | 58 ++++++ ee4363/mp1/mp11/out | 152 ++++++++++++++++ ee4363/mp1/mp11/test_mipsalu.v | 49 +++++ ee4363/mp1/mp12/mipspipe.v | 93 ++++++++++ ee4363/mp1/mp12/out | 369 ++++++++++++++++++++++++++++++++++++++ ee4363/mp1/mp12/test_mipspipe.v | 53 ++++++ ee4363/mp1/mp12/test_mipspipe.vcd | 267 +++++++++++++++++++++++++++ ee4363/mp1/out | 152 ---------------- ee4363/mp1/test_mipsalu.v | 49 ----- ee4363/mp1/test_mipspipe.v | 53 ------ 14 files changed, 1059 insertions(+), 419 deletions(-) delete mode 100644 ee4363/mp1/MIPSALU.v delete mode 100644 ee4363/mp1/MIPSAlu.vcd delete mode 100644 ee4363/mp1/mipspipe.v create mode 100644 ee4363/mp1/mp11/MIPSALU.v create mode 100644 ee4363/mp1/mp11/MIPSAlu.vcd create mode 100644 ee4363/mp1/mp11/out create mode 100644 ee4363/mp1/mp11/test_mipsalu.v create mode 100644 ee4363/mp1/mp12/mipspipe.v create mode 100644 ee4363/mp1/mp12/out create mode 100644 ee4363/mp1/mp12/test_mipspipe.v create mode 100644 ee4363/mp1/mp12/test_mipspipe.vcd delete mode 100644 ee4363/mp1/out delete mode 100644 ee4363/mp1/test_mipsalu.v delete mode 100644 ee4363/mp1/test_mipspipe.v (limited to 'ee4363/mp1') diff --git a/ee4363/mp1/MIPSALU.v b/ee4363/mp1/MIPSALU.v deleted file mode 100644 index 096aff5..0000000 --- a/ee4363/mp1/MIPSALU.v +++ /dev/null @@ -1,18 +0,0 @@ -module MIPSALU (ALUctl, A, B, ALUOut, Zero); - input [3:0] ALUctl; - input [31:0] A,B; - output reg [31:0] ALUOut; - output Zero; - assign Zero = (ALUOut==0); - always @(ALUctl, A, B) - case (ALUctl) - 0: ALUOut <= A & B; - 1: ALUOut <= A | B; - 2: ALUOut <= A + B; - 6: ALUOut <= A - B; - 7: ALUOut <= A < B ? 1:0; - 12: ALUOut <= ~(A | B); - default: ALUOut <= 0; - endcase -endmodule - diff --git a/ee4363/mp1/MIPSAlu.vcd b/ee4363/mp1/MIPSAlu.vcd deleted file mode 100644 index e20e5e6..0000000 --- a/ee4363/mp1/MIPSAlu.vcd +++ /dev/null @@ -1,57 +0,0 @@ -$date - Sat Nov 21 15:12:24 2020 -$end -$version - Icarus Verilog -$end -$timescale - 100ps -$end -$scope module test_mipsalu $end -$var wire 1 ! Zero $end -$var wire 32 " ALUOut [31:0] $end -$var reg 32 # A [31:0] $end -$var reg 4 $ ALUctl [3:0] $end -$var reg 32 % B [31:0] $end -$scope module U0 $end -$var wire 32 & A [31:0] $end -$var wire 4 ' ALUctl [3:0] $end -$var wire 32 ( B [31:0] $end -$var wire 1 ! Zero $end -$var reg 32 ) ALUOut [31:0] $end -$upscope $end -$upscope $end -$enddefinitions $end -#0 -$dumpvars -b0 ) -b1010101010101010101010101010101 ( -bx ' -b1010101010101010101010101010101 & -b1010101010101010101010101010101 % -bx $ -b1010101010101010101010101010101 # -b0 " -1! -$end -#100 -0! -b1010101010101010101010101010101 " -b1010101010101010101010101010101 ) -b0 $ -b0 ' -#200 -b1 $ -b1 ' -#300 -b10101010101010101010101010101010 " -b10101010101010101010101010101010 ) -b10 $ -b10 ' -#400 -1! -b0 " -b0 ) -b110 $ -b110 ' -#500 diff --git a/ee4363/mp1/mipspipe.v b/ee4363/mp1/mipspipe.v deleted file mode 100644 index 951bde0..0000000 --- a/ee4363/mp1/mipspipe.v +++ /dev/null @@ -1,90 +0,0 @@ -// Incomplete behavioral model of MIPS pipeline - -module mipspipe(clock); - // in_out - input clock; - - // Instruction opcodes - parameter LW = 6'b100011, SW = 6'b101011, BEQ = 6'b000100, nop = 32'b00000_100000, ALUop = 6'b0; - reg [31:0] PC, // Program counter - Regs[0:31], // Register file - IMemory[0:1023], DMemory[0:1023], // Instruction and data memories - IFIDIR, IDEXA, IDEXB, IDEXIR, EXMEMIR, EXMEMB, // pipeline latches - EXMEMALUOut, MEMWBValue, MEMWBIR; // pipeline latches - - wire [4:0] IDEXrs, IDEXrt, EXMEMrd, MEMWBrd, MEMWBrt; // fields of pipeline latches - wire [5:0] EXMEMop, MEMWBop, IDEXop; // opcodes - wire [31:0] Ain, Bin; // ALU inputs - - // Define fields of pipeline latches - assign IDEXrs = IDEXIR[25:21]; // rs field - assign IDEXrt = IDEXIR[20:16]; // rt field - assign EXMEMrd = EXMEMIR[15:11]; // rd field - assign MEMWBrd = MEMWBIR[15:11]; // rd field - assign MEMWBrt = MEMWBIR[20:16]; // rt field -- for loads - assign EXMEMop = EXMEMIR[31:26]; // opcode - assign MEMWBop = MEMWBIR[31:26]; // opcode - assign IDEXop = IDEXIR[31:26]; // opcode - - // Inputs to the ALU come directly from the ID/EX pipeline latches - assign Ain = IDEXA; - assign Bin = IDEXB; - reg [5:0] i; //used to initialize registers - reg [10:0] j,k; //used to initialize registers - - initial begin - PC = 0; - IFIDIR = nop; - IDEXIR = nop; - EXMEMIR = nop; - MEMWBIR = nop; // no-ops placed in pipeline latches - // test some instructions - for (i=0;i<=31;i=i+1) Regs[i] = i; // initialize registers - IMemory[0] = 32'h8c210003; - IMemory[1] = 32'hac020000; - IMemory[2] = 32'h00642820; - for (j=3;j<=1023;j=j+1) IMemory[j] = nop; - DMemory[0] = 32'h00000000; - DMemory[1] = 32'hffffffff; - for (k=2;k<=1023;k=k+1) DMemory[k] = 0; - end - - always @ (posedge clock) - begin - // FETCH: Fetch instruction & update PC - IFIDIR <= IMemory[PC>>2]; - PC <= PC + 4; - - // DECODE: Read registers - IDEXA <= Regs[IFIDIR[25:21]]; - IDEXB <= Regs[IFIDIR[20:16]]; // get two registers - - IDEXIR <= IFIDIR; // pass along IR - - // EX: Address calculation or ALU operation - if ((IDEXop==LW) |(IDEXop==SW)) // address calculation - EXMEMALUOut <= IDEXA +{{16{IDEXIR[15]}}, IDEXIR[15:0]}; - else if (IDEXop==ALUop) begin // ALU operation - case (IDEXIR[5:0]) // R-type instruction - 32: EXMEMALUOut <= Ain + Bin; // add operation - default: ; // other R-type operations [to be implemented] - endcase - end - - EXMEMIR <= IDEXIR; EXMEMB <= IDEXB; //pass along the IR & B - - // MEM - if (EXMEMop==ALUop) MEMWBValue <= EXMEMALUOut; //pass along ALU result - else if (EXMEMop == LW) MEMWBValue <= DMemory[EXMEMALUOut>>2]; // load - else if (EXMEMop == SW) DMemory[EXMEMALUOut>>2] <=EXMEMB; // store - - MEMWBIR <= EXMEMIR; //pass along IR - - // WB - if ((MEMWBop==ALUop) & (MEMWBrd != 0)) // update registers if ALU operation and destination not 0 - Regs[MEMWBrd] <= MEMWBValue; // ALU operation - else if ((MEMWBop == LW)& (MEMWBrt != 0)) // Update registers if load and destination not 0 - Regs[MEMWBrt] <= MEMWBValue; - end - -endmodule diff --git a/ee4363/mp1/mp11/MIPSALU.v b/ee4363/mp1/mp11/MIPSALU.v new file mode 100644 index 0000000..096aff5 --- /dev/null +++ b/ee4363/mp1/mp11/MIPSALU.v @@ -0,0 +1,18 @@ +module MIPSALU (ALUctl, A, B, ALUOut, Zero); + input [3:0] ALUctl; + input [31:0] A,B; + output reg [31:0] ALUOut; + output Zero; + assign Zero = (ALUOut==0); + always @(ALUctl, A, B) + case (ALUctl) + 0: ALUOut <= A & B; + 1: ALUOut <= A | B; + 2: ALUOut <= A + B; + 6: ALUOut <= A - B; + 7: ALUOut <= A < B ? 1:0; + 12: ALUOut <= ~(A | B); + default: ALUOut <= 0; + endcase +endmodule + diff --git a/ee4363/mp1/mp11/MIPSAlu.vcd b/ee4363/mp1/mp11/MIPSAlu.vcd new file mode 100644 index 0000000..b81fdb8 --- /dev/null +++ b/ee4363/mp1/mp11/MIPSAlu.vcd @@ -0,0 +1,58 @@ +$date + Thu Dec 3 09:43:49 2020 +$end +$version + Icarus Verilog +$end +$timescale + 100ps +$end +$scope module test_mipsalu $end +$var wire 1 ! Zero $end +$var wire 32 " ALUOut [31:0] $end +$var reg 32 # A [31:0] $end +$var reg 4 $ ALUctl [3:0] $end +$var reg 32 % B [31:0] $end +$scope module U0 $end +$var wire 32 & A [31:0] $end +$var wire 4 ' ALUctl [3:0] $end +$var wire 32 ( B [31:0] $end +$var wire 1 ! Zero $end +$var reg 32 ) ALUOut [31:0] $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +b0 ) +b1 ( +bx ' +b1111 & +b1 % +bx $ +b1111 # +b0 " +1! +$end +#100 +0! +b1 " +b1 ) +b0 $ +b0 ' +#200 +b1111 " +b1111 ) +b1 $ +b1 ' +#300 +b10000 " +b10000 ) +b10 $ +b10 ' +#400 +b1110 " +b1110 ) +b110 $ +b110 ' +#500 diff --git a/ee4363/mp1/mp11/out b/ee4363/mp1/mp11/out new file mode 100644 index 0000000..b09d3dc --- /dev/null +++ b/ee4363/mp1/mp11/out @@ -0,0 +1,152 @@ +#! /usr/bin/vvp +:ivl_version "10.3 (stable)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision - 10; +:vpi_module "system"; +:vpi_module "vhdl_sys"; +:vpi_module "v2005_math"; +:vpi_module "va_math"; +S_0x5600cdc34d10 .scope module, "test_mipsalu" "test_mipsalu" 2 8; + .timescale -9 -10; +v0x5600cdc4a050_0 .var "A", 31 0; +v0x5600cdc4a130_0 .net "ALUOut", 31 0, v0x5600cdc49b10_0; 1 drivers +v0x5600cdc4a200_0 .var "ALUctl", 3 0; +v0x5600cdc4a300_0 .var "B", 31 0; +v0x5600cdc4a3d0_0 .net "Zero", 0 0, L_0x5600cdc5a530; 1 drivers +S_0x5600cdc34e90 .scope module, "U0" "MIPSALU" 2 19, 3 1 0, S_0x5600cdc34d10; + .timescale -9 -10; + .port_info 0 /INPUT 4 "ALUctl" + .port_info 1 /INPUT 32 "A" + .port_info 2 /INPUT 32 "B" + .port_info 3 /OUTPUT 32 "ALUOut" + .port_info 4 /OUTPUT 1 "Zero" +v0x5600cdbfd130_0 .net "A", 31 0, v0x5600cdc4a050_0; 1 drivers +v0x5600cdc49b10_0 .var "ALUOut", 31 0; +v0x5600cdc49bf0_0 .net "ALUctl", 3 0, v0x5600cdc4a200_0; 1 drivers +v0x5600cdc49ce0_0 .net "B", 31 0, v0x5600cdc4a300_0; 1 drivers +v0x5600cdc49dc0_0 .net "Zero", 0 0, L_0x5600cdc5a530; alias, 1 drivers +L_0x7f1879ed6018 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x5600cdc49ed0_0 .net/2u *"_s0", 31 0, L_0x7f1879ed6018; 1 drivers +E_0x5600cdc327b0 .event edge, v0x5600cdc49ce0_0, v0x5600cdbfd130_0, v0x5600cdc49bf0_0; +L_0x5600cdc5a530 .cmp/eq 32, v0x5600cdc49b10_0, L_0x7f1879ed6018; + .scope S_0x5600cdc34e90; +T_0 ; + %wait E_0x5600cdc327b0; + %load/vec4 v0x5600cdc49bf0_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_0.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_0.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_0.2, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_0.3, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_0.4, 6; + %dup/vec4; + %pushi/vec4 12, 0, 4; + %cmp/u; + %jmp/1 T_0.5, 6; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x5600cdc49b10_0, 0; + %jmp T_0.7; +T_0.0 ; + %load/vec4 v0x5600cdbfd130_0; + %load/vec4 v0x5600cdc49ce0_0; + %and; + %assign/vec4 v0x5600cdc49b10_0, 0; + %jmp T_0.7; +T_0.1 ; + %load/vec4 v0x5600cdbfd130_0; + %load/vec4 v0x5600cdc49ce0_0; + %or; + %assign/vec4 v0x5600cdc49b10_0, 0; + %jmp T_0.7; +T_0.2 ; + %load/vec4 v0x5600cdbfd130_0; + %load/vec4 v0x5600cdc49ce0_0; + %add; + %assign/vec4 v0x5600cdc49b10_0, 0; + %jmp T_0.7; +T_0.3 ; + %load/vec4 v0x5600cdbfd130_0; + %load/vec4 v0x5600cdc49ce0_0; + %sub; + %assign/vec4 v0x5600cdc49b10_0, 0; + %jmp T_0.7; +T_0.4 ; + %load/vec4 v0x5600cdbfd130_0; + %load/vec4 v0x5600cdc49ce0_0; + %cmp/u; + %flag_mov 8, 5; + %jmp/0 T_0.8, 8; + %pushi/vec4 1, 0, 32; + %jmp/1 T_0.9, 8; +T_0.8 ; End of true expr. + %pushi/vec4 0, 0, 32; + %jmp/0 T_0.9, 8; + ; End of false expr. + %blend; +T_0.9; + %assign/vec4 v0x5600cdc49b10_0, 0; + %jmp T_0.7; +T_0.5 ; + %load/vec4 v0x5600cdbfd130_0; + %load/vec4 v0x5600cdc49ce0_0; + %or; + %inv; + %assign/vec4 v0x5600cdc49b10_0, 0; + %jmp T_0.7; +T_0.7 ; + %pop/vec4 1; + %jmp T_0; + .thread T_0, $push; + .scope S_0x5600cdc34d10; +T_1 ; + %pushi/vec4 15, 0, 32; + %store/vec4 v0x5600cdc4a050_0, 0, 32; + %pushi/vec4 1, 0, 32; + %store/vec4 v0x5600cdc4a300_0, 0, 32; + %delay 100, 0; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x5600cdc4a200_0, 0, 4; + %delay 100, 0; + %pushi/vec4 1, 0, 4; + %store/vec4 v0x5600cdc4a200_0, 0, 4; + %delay 100, 0; + %pushi/vec4 2, 0, 4; + %store/vec4 v0x5600cdc4a200_0, 0, 4; + %delay 100, 0; + %pushi/vec4 6, 0, 4; + %store/vec4 v0x5600cdc4a200_0, 0, 4; + %delay 100, 0; + %vpi_call 2 32 "$finish" {0 0 0}; + %end; + .thread T_1; + .scope S_0x5600cdc34d10; +T_2 ; + %vpi_call 2 38 "$monitor", $time, " A = %h", v0x5600cdc4a050_0, " B = %h", v0x5600cdc4a300_0, " ALUOut = %h", v0x5600cdc4a130_0, " Zero = %b", v0x5600cdc4a3d0_0 {0 0 0}; + %end; + .thread T_2; + .scope S_0x5600cdc34d10; +T_3 ; + %vpi_call 2 43 "$dumpfile", "MIPSAlu.vcd" {0 0 0}; + %vpi_call 2 44 "$dumpvars" {0 0 0}; + %end; + .thread T_3; +# The file index is used to find the file name in the following table. +:file_names 4; + "N/A"; + ""; + "test_mipsalu.v"; + "./MIPSALU.v"; diff --git a/ee4363/mp1/mp11/test_mipsalu.v b/ee4363/mp1/mp11/test_mipsalu.v new file mode 100644 index 0000000..9738ed5 --- /dev/null +++ b/ee4363/mp1/mp11/test_mipsalu.v @@ -0,0 +1,49 @@ + `timescale 1ns/100ps +// +// Test Bench for the mips alu +// T. Posbergh, 14 October 2012 +// + `include "MIPSALU.v" +// +module test_mipsalu; + wire Zero; // ALU bit output + wire [31:0] ALUOut; // ALU word output + reg [31:0] A,B; // ALU word inpus + reg [3:0] ALUctl; + + reg clock; + reg reset; + +// instantiate the alu and control + + MIPSALU U0(ALUctl, A, B, ALUOut, Zero); + +// generate test signals + + initial + begin + A=32'b0000_0000_0000_0000_0000_0000_0000_1111; + B=32'b0000_0000_0000_0000_0000_0000_0000_0001; + #10 ALUctl=4'b0000; + #10 ALUctl=4'b0001; + #10 ALUctl=4'b0010; + #10 ALUctl=4'b0110; +// $finish(100); + #10 $finish; + end + +// output result + + initial + $monitor($time, " A = %h",A," B = %h",B," ALUOut = %h",ALUOut," Zero = %b",Zero); + +// the following generates vcd file for GTKwave + initial + begin + $dumpfile("MIPSAlu.vcd"); + $dumpvars; + end + +endmodule + + diff --git a/ee4363/mp1/mp12/mipspipe.v b/ee4363/mp1/mp12/mipspipe.v new file mode 100644 index 0000000..62b4e8b --- /dev/null +++ b/ee4363/mp1/mp12/mipspipe.v @@ -0,0 +1,93 @@ +// Incomplete behavioral model of MIPS pipeline + +module mipspipe(clock); + // in_out + input clock; + + // Instruction opcodes + parameter LW = 6'b100011, SW = 6'b101011, BEQ = 6'b000100, nop = 32'b00000_100000, ALUop = 6'b0; + reg [31:0] PC, // Program counter + Regs[0:31], // Register file + IMemory[0:1023], DMemory[0:1023], // Instruction and data memories + IFIDIR, IDEXA, IDEXB, IDEXIR, EXMEMIR, EXMEMB, // pipeline latches + EXMEMALUOut, MEMWBValue, MEMWBIR; // pipeline latches + + wire [4:0] IDEXrs, IDEXrt, EXMEMrd, MEMWBrd, MEMWBrt; // fields of pipeline latches + wire [5:0] EXMEMop, MEMWBop, IDEXop; // opcodes + wire [31:0] Ain, Bin; // ALU inputs + + // Define fields of pipeline latches + assign IDEXrs = IDEXIR[25:21]; // rs field + assign IDEXrt = IDEXIR[20:16]; // rt field + assign EXMEMrd = EXMEMIR[15:11]; // rd field + assign MEMWBrd = MEMWBIR[15:11]; // rd field + assign MEMWBrt = MEMWBIR[20:16]; // rt field -- for loads + assign EXMEMop = EXMEMIR[31:26]; // opcode + assign MEMWBop = MEMWBIR[31:26]; // opcode + assign IDEXop = IDEXIR[31:26]; // opcode + + // Inputs to the ALU come directly from the ID/EX pipeline latches + assign Ain = IDEXA; + assign Bin = IDEXB; + reg [5:0] i; //used to initialize registers + reg [10:0] j,k; //used to initialize registers + + initial begin + PC = 0; + IFIDIR = nop; + IDEXIR = nop; + EXMEMIR = nop; + MEMWBIR = nop; // no-ops placed in pipeline latches + // test some instructions + for (i=0;i<=31;i=i+1) Regs[i] = i; // initialize registers +IMemory[0] = 32'h00412820; // ADD OPCODE: 000000 00010 00001 00101 00000 100000 + IMemory[1] = 32'h8CA30004; // First LW: 100011 00101 00011 00000 00000 00 0100 + IMemory[2] = 32'h8C420000; // Second LW: 100011 00010 00010 00000 00000 000000 + IMemory[3] = 32'h00A31825; // OR OPCODE: 000000 00101 00011 00011 00000 100101 + IMemory[4] = 32'hACA30000; // SW: 101011 00101 00011 00000 00000 000000 + for (j=5;j<=1023;j=j+1) IMemory[j] = nop; + DMemory[0] = 32'h00000000; + DMemory[1] = 32'hffffffff; + for (k=2;k<=1023;k=k+1) DMemory[k] = 0; + end + + always @ (posedge clock) + begin + // FETCH: Fetch instruction & update PC + IFIDIR <= IMemory[PC>>2]; + PC <= PC + 4; + + // DECODE: Read registers + IDEXA <= Regs[IFIDIR[25:21]]; + IDEXB <= Regs[IFIDIR[20:16]]; // get two registers + + IDEXIR <= IFIDIR; // pass along IR + + // EX: Address calculation or ALU operation + if ((IDEXop==LW) |(IDEXop==SW)) // address calculation + EXMEMALUOut <= IDEXA +{{16{IDEXIR[15]}}, IDEXIR[15:0]}; + else if (IDEXop==ALUop) begin // ALU operation + case (IDEXIR[5:0]) // R-type instruction + 32: EXMEMALUOut <= Ain + Bin; // add operation + 37: EXMEMALUOut <= Ain | Bin; //or + default: ; // other R-type operations [to be implemented] + endcase + end + + EXMEMIR <= IDEXIR; EXMEMB <= IDEXB; //pass along the IR & B + + // MEM + if (EXMEMop==ALUop) MEMWBValue <= EXMEMALUOut; //pass along ALU result + else if (EXMEMop == LW) MEMWBValue <= DMemory[EXMEMALUOut>>2]; // load + else if (EXMEMop == SW) DMemory[EXMEMALUOut>>2] <=EXMEMB; // store + + MEMWBIR <= EXMEMIR; //pass along IR + + // WB + if ((MEMWBop==ALUop) & (MEMWBrd != 0)) // update registers if ALU operation and destination not 0 + Regs[MEMWBrd] <= MEMWBValue; // ALU operation + else if ((MEMWBop == LW)& (MEMWBrt != 0)) // Update registers if load and destination not 0 + Regs[MEMWBrt] <= MEMWBValue; + end + +endmodule diff --git a/ee4363/mp1/mp12/out b/ee4363/mp1/mp12/out new file mode 100644 index 0000000..91338a7 --- /dev/null +++ b/ee4363/mp1/mp12/out @@ -0,0 +1,369 @@ +#! /usr/bin/vvp +:ivl_version "10.3 (stable)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision + 0; +:vpi_module "system"; +:vpi_module "vhdl_sys"; +:vpi_module "v2005_math"; +:vpi_module "va_math"; +S_0x55a34db03e40 .scope module, "test_mipspipe" "test_mipspipe" 2 8; + .timescale 0 0; +v0x55a34db449f0_0 .var "clock", 0 0; +v0x55a34db44a90_0 .var "clock_cycle", 3 0; +E_0x55a34db17f80 .event negedge, v0x55a34db44650_0; +S_0x55a34db039a0 .scope module, "u_mipspipe" "mipspipe" 2 14, 3 3 0, S_0x55a34db03e40; + .timescale 0 0; + .port_info 0 /INPUT 1 "clock" +P_0x55a34db042e0 .param/l "ALUop" 0 3 8, C4<000000>; +P_0x55a34db04320 .param/l "BEQ" 0 3 8, C4<000100>; +P_0x55a34db04360 .param/l "LW" 0 3 8, C4<100011>; +P_0x55a34db043a0 .param/l "SW" 0 3 8, C4<101011>; +P_0x55a34db043e0 .param/l "nop" 0 3 8, C4<00000000000000000000000000100000>; +L_0x55a34dadea40 .functor BUFZ 32, v0x55a34db43970_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x55a34dade820 .functor BUFZ 32, v0x55a34db43a50_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +v0x55a34db0c970_0 .net "Ain", 31 0, L_0x55a34dadea40; 1 drivers +v0x55a34db43340_0 .net "Bin", 31 0, L_0x55a34dade820; 1 drivers +v0x55a34db43420 .array "DMemory", 1023 0, 31 0; +v0x55a34db434c0_0 .var "EXMEMALUOut", 31 0; +v0x55a34db435a0_0 .var "EXMEMB", 31 0; +v0x55a34db436d0_0 .var "EXMEMIR", 31 0; +v0x55a34db437b0_0 .net "EXMEMop", 5 0, L_0x55a34db44fb0; 1 drivers +v0x55a34db43890_0 .net "EXMEMrd", 4 0, L_0x55a34db44c90; 1 drivers +v0x55a34db43970_0 .var "IDEXA", 31 0; +v0x55a34db43a50_0 .var "IDEXB", 31 0; +v0x55a34db43b30_0 .var "IDEXIR", 31 0; +v0x55a34db43c10_0 .net "IDEXop", 5 0, L_0x55a34db45180; 1 drivers +v0x55a34db43cf0_0 .net "IDEXrs", 4 0, L_0x55a34db44b50; 1 drivers +v0x55a34db43dd0_0 .net "IDEXrt", 4 0, L_0x55a34db44bf0; 1 drivers +v0x55a34db43eb0_0 .var "IFIDIR", 31 0; +v0x55a34db43f90 .array "IMemory", 1023 0, 31 0; +v0x55a34db44050_0 .var "MEMWBIR", 31 0; +v0x55a34db44130_0 .var "MEMWBValue", 31 0; +v0x55a34db44210_0 .net "MEMWBop", 5 0, L_0x55a34db450e0; 1 drivers +v0x55a34db442f0_0 .net "MEMWBrd", 4 0, L_0x55a34db44d60; 1 drivers +v0x55a34db443d0_0 .net "MEMWBrt", 4 0, L_0x55a34db44e90; 1 drivers +v0x55a34db444b0_0 .var "PC", 31 0; +v0x55a34db44590 .array "Regs", 31 0, 31 0; +v0x55a34db44650_0 .net "clock", 0 0, v0x55a34db449f0_0; 1 drivers +v0x55a34db44710_0 .var "i", 5 0; +v0x55a34db447f0_0 .var "j", 10 0; +v0x55a34db448d0_0 .var "k", 10 0; +E_0x55a34db18270 .event posedge, v0x55a34db44650_0; +L_0x55a34db44b50 .part v0x55a34db43b30_0, 21, 5; +L_0x55a34db44bf0 .part v0x55a34db43b30_0, 16, 5; +L_0x55a34db44c90 .part v0x55a34db436d0_0, 11, 5; +L_0x55a34db44d60 .part v0x55a34db44050_0, 11, 5; +L_0x55a34db44e90 .part v0x55a34db44050_0, 16, 5; +L_0x55a34db44fb0 .part v0x55a34db436d0_0, 26, 6; +L_0x55a34db450e0 .part v0x55a34db44050_0, 26, 6; +L_0x55a34db45180 .part v0x55a34db43b30_0, 26, 6; + .scope S_0x55a34db039a0; +T_0 ; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x55a34db444b0_0, 0, 32; + %pushi/vec4 32, 0, 32; + %store/vec4 v0x55a34db43eb0_0, 0, 32; + %pushi/vec4 32, 0, 32; + %store/vec4 v0x55a34db43b30_0, 0, 32; + %pushi/vec4 32, 0, 32; + %store/vec4 v0x55a34db436d0_0, 0, 32; + %pushi/vec4 32, 0, 32; + %store/vec4 v0x55a34db44050_0, 0, 32; + %pushi/vec4 0, 0, 6; + %store/vec4 v0x55a34db44710_0, 0, 6; +T_0.0 ; + %load/vec4 v0x55a34db44710_0; + %pad/u 32; + %cmpi/u 31, 0, 32; + %flag_or 5, 4; + %jmp/0xz T_0.1, 5; + %load/vec4 v0x55a34db44710_0; + %pad/u 32; + %load/vec4 v0x55a34db44710_0; + %pad/u 7; + %ix/vec4 4; + %store/vec4a v0x55a34db44590, 4, 0; + %load/vec4 v0x55a34db44710_0; + %addi 1, 0, 6; + %store/vec4 v0x55a34db44710_0, 0, 6; + %jmp T_0.0; +T_0.1 ; + %pushi/vec4 4270112, 0, 32; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x55a34db43f90, 4, 0; + %pushi/vec4 2359492612, 0, 32; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x55a34db43f90, 4, 0; + %pushi/vec4 2353135616, 0, 32; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x55a34db43f90, 4, 0; + %pushi/vec4 10688549, 0, 32; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x55a34db43f90, 4, 0; + %pushi/vec4 2896363520, 0, 32; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x55a34db43f90, 4, 0; + %pushi/vec4 5, 0, 11; + %store/vec4 v0x55a34db447f0_0, 0, 11; +T_0.2 ; + %load/vec4 v0x55a34db447f0_0; + %pad/u 32; + %cmpi/u 1023, 0, 32; + %flag_or 5, 4; + %jmp/0xz T_0.3, 5; + %pushi/vec4 32, 0, 32; + %load/vec4 v0x55a34db447f0_0; + %pad/u 12; + %ix/vec4 4; + %store/vec4a v0x55a34db43f90, 4, 0; + %load/vec4 v0x55a34db447f0_0; + %addi 1, 0, 11; + %store/vec4 v0x55a34db447f0_0, 0, 11; + %jmp T_0.2; +T_0.3 ; + %pushi/vec4 0, 0, 32; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x55a34db43420, 4, 0; + %pushi/vec4 4294967295, 0, 32; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x55a34db43420, 4, 0; + %pushi/vec4 2, 0, 11; + %store/vec4 v0x55a34db448d0_0, 0, 11; +T_0.4 ; + %load/vec4 v0x55a34db448d0_0; + %pad/u 32; + %cmpi/u 1023, 0, 32; + %flag_or 5, 4; + %jmp/0xz T_0.5, 5; + %pushi/vec4 0, 0, 32; + %load/vec4 v0x55a34db448d0_0; + %pad/u 12; + %ix/vec4 4; + %store/vec4a v0x55a34db43420, 4, 0; + %load/vec4 v0x55a34db448d0_0; + %addi 1, 0, 11; + %store/vec4 v0x55a34db448d0_0, 0, 11; + %jmp T_0.4; +T_0.5 ; + %end; + .thread T_0; + .scope S_0x55a34db039a0; +T_1 ; + %wait E_0x55a34db18270; + %load/vec4 v0x55a34db444b0_0; + %ix/load 5, 2, 0; + %flag_set/imm 4, 0; + %shiftr 5; + %ix/vec4 4; + %load/vec4a v0x55a34db43f90, 4; + %assign/vec4 v0x55a34db43eb0_0, 0; + %load/vec4 v0x55a34db444b0_0; + %addi 4, 0, 32; + %assign/vec4 v0x55a34db444b0_0, 0; + %load/vec4 v0x55a34db43eb0_0; + %parti/s 5, 21, 6; + %pad/u 7; + %ix/vec4 4; + %load/vec4a v0x55a34db44590, 4; + %assign/vec4 v0x55a34db43970_0, 0; + %load/vec4 v0x55a34db43eb0_0; + %parti/s 5, 16, 6; + %pad/u 7; + %ix/vec4 4; + %load/vec4a v0x55a34db44590, 4; + %assign/vec4 v0x55a34db43a50_0, 0; + %load/vec4 v0x55a34db43eb0_0; + %assign/vec4 v0x55a34db43b30_0, 0; + %load/vec4 v0x55a34db43c10_0; + %pushi/vec4 35, 0, 6; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x55a34db43c10_0; + %pushi/vec4 43, 0, 6; + %cmp/e; + %flag_get/vec4 4; + %or; + %flag_set/vec4 8; + %jmp/0xz T_1.0, 8; + %load/vec4 v0x55a34db43970_0; + %load/vec4 v0x55a34db43b30_0; + %parti/s 1, 15, 5; + %replicate 16; + %load/vec4 v0x55a34db43b30_0; + %parti/s 16, 0, 2; + %concat/vec4; draw_concat_vec4 + %add; + %assign/vec4 v0x55a34db434c0_0, 0; + %jmp T_1.1; +T_1.0 ; + %load/vec4 v0x55a34db43c10_0; + %cmpi/e 0, 0, 6; + %jmp/0xz T_1.2, 4; + %load/vec4 v0x55a34db43b30_0; + %parti/s 6, 0, 2; + %dup/vec4; + %pushi/vec4 32, 0, 6; + %cmp/u; + %jmp/1 T_1.4, 6; + %dup/vec4; + %pushi/vec4 37, 0, 6; + %cmp/u; + %jmp/1 T_1.5, 6; + %jmp T_1.7; +T_1.4 ; + %load/vec4 v0x55a34db0c970_0; + %load/vec4 v0x55a34db43340_0; + %add; + %assign/vec4 v0x55a34db434c0_0, 0; + %jmp T_1.7; +T_1.5 ; + %load/vec4 v0x55a34db0c970_0; + %load/vec4 v0x55a34db43340_0; + %or; + %assign/vec4 v0x55a34db434c0_0, 0; + %jmp T_1.7; +T_1.7 ; + %pop/vec4 1; +T_1.2 ; +T_1.1 ; + %load/vec4 v0x55a34db43b30_0; + %assign/vec4 v0x55a34db436d0_0, 0; + %load/vec4 v0x55a34db43a50_0; + %assign/vec4 v0x55a34db435a0_0, 0; + %load/vec4 v0x55a34db437b0_0; + %cmpi/e 0, 0, 6; + %jmp/0xz T_1.8, 4; + %load/vec4 v0x55a34db434c0_0; + %assign/vec4 v0x55a34db44130_0, 0; + %jmp T_1.9; +T_1.8 ; + %load/vec4 v0x55a34db437b0_0; + %cmpi/e 35, 0, 6; + %jmp/0xz T_1.10, 4; + %load/vec4 v0x55a34db434c0_0; + %ix/load 5, 2, 0; + %flag_set/imm 4, 0; + %shiftr 5; + %ix/vec4 4; + %load/vec4a v0x55a34db43420, 4; + %assign/vec4 v0x55a34db44130_0, 0; + %jmp T_1.11; +T_1.10 ; + %load/vec4 v0x55a34db437b0_0; + %cmpi/e 43, 0, 6; + %jmp/0xz T_1.12, 4; + %load/vec4 v0x55a34db435a0_0; + %load/vec4 v0x55a34db434c0_0; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %shiftr 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x55a34db43420, 0, 4; +T_1.12 ; +T_1.11 ; +T_1.9 ; + %load/vec4 v0x55a34db436d0_0; + %assign/vec4 v0x55a34db44050_0, 0; + %load/vec4 v0x55a34db44210_0; + %pushi/vec4 0, 0, 6; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x55a34db442f0_0; + %pad/u 32; + %pushi/vec4 0, 0, 32; + %cmp/e; + %flag_get/vec4 4; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_1.14, 8; + %load/vec4 v0x55a34db44130_0; + %load/vec4 v0x55a34db442f0_0; + %pad/u 7; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x55a34db44590, 0, 4; + %jmp T_1.15; +T_1.14 ; + %load/vec4 v0x55a34db44210_0; + %pushi/vec4 35, 0, 6; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x55a34db443d0_0; + %pad/u 32; + %pushi/vec4 0, 0, 32; + %cmp/e; + %flag_get/vec4 4; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_1.16, 8; + %load/vec4 v0x55a34db44130_0; + %load/vec4 v0x55a34db443d0_0; + %pad/u 7; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x55a34db44590, 0, 4; +T_1.16 ; +T_1.15 ; + %jmp T_1; + .thread T_1; + .scope S_0x55a34db03e40; +T_2 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x55a34db449f0_0, 0, 1; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x55a34db44a90_0, 0, 4; + %delay 160, 0; + %vpi_call 2 20 "$finish" {0 0 0}; + %end; + .thread T_2; + .scope S_0x55a34db03e40; +T_3 ; + %delay 5, 0; + %load/vec4 v0x55a34db449f0_0; + %inv; + %store/vec4 v0x55a34db449f0_0, 0, 1; + %jmp T_3; + .thread T_3; + .scope S_0x55a34db03e40; +T_4 ; + %wait E_0x55a34db18270; + %load/vec4 v0x55a34db44a90_0; + %addi 1, 0, 4; + %store/vec4 v0x55a34db44a90_0, 0, 4; + %jmp T_4; + .thread T_4; + .scope S_0x55a34db03e40; +T_5 ; + %wait E_0x55a34db17f80; + %vpi_call 2 36 "$display", "\012\012clock cycle = %d", v0x55a34db44a90_0, " (time = %1.0t)", $time {0 0 0}; + %vpi_call 2 37 "$display", "IF/ID registers\012\011 IF/ID.PC+4 = %h, IF/ID.IR = %h \012", v0x55a34db444b0_0, v0x55a34db43eb0_0 {0 0 0}; + %vpi_call 2 38 "$display", "ID/EX registers\012\011 ID/EX.rs = %d, ID/EX.rt = %d", v0x55a34db43cf0_0, v0x55a34db43dd0_0, "\012\011 ID/EX.A = %h, ID/EX.B = %h", v0x55a34db43970_0, v0x55a34db43a50_0 {0 0 0}; + %vpi_call 2 39 "$display", "\011 ID/EX.op = %h\012", v0x55a34db43c10_0 {0 0 0}; + %vpi_call 2 40 "$display", "EX/MEM registers\012\011 EX/MEM.rs = %d, EX/MEM.rt = %d", v0x55a34db43cf0_0, v0x55a34db43dd0_0, "\012\011 EX/MEM.ALUOut = %h, EX/MEM.ALUout = %h", v0x55a34db434c0_0, v0x55a34db435a0_0 {0 0 0}; + %vpi_call 2 41 "$display", "\011 EX/MEM.op = %h\012", v0x55a34db437b0_0 {0 0 0}; + %vpi_call 2 42 "$display", "MEM/WB registers\012\011 MEM/WB.rd = %d, MEM/WB.rt = %d", v0x55a34db442f0_0, v0x55a34db443d0_0, "\012\011 MEM/WB.value = %h", v0x55a34db44130_0 {0 0 0}; + %vpi_call 2 43 "$display", "\011 EX/MEM.op = %h\012", v0x55a34db44210_0 {0 0 0}; + %jmp T_5; + .thread T_5; + .scope S_0x55a34db03e40; +T_6 ; + %vpi_call 2 49 "$dumpfile", "test_mipspipe.vcd" {0 0 0}; + %vpi_call 2 50 "$dumpvars" {0 0 0}; + %end; + .thread T_6; +# The file index is used to find the file name in the following table. +:file_names 4; + "N/A"; + ""; + "test_mipspipe.v"; + "./mipspipe.v"; diff --git a/ee4363/mp1/mp12/test_mipspipe.v b/ee4363/mp1/mp12/test_mipspipe.v new file mode 100644 index 0000000..24576ec --- /dev/null +++ b/ee4363/mp1/mp12/test_mipspipe.v @@ -0,0 +1,53 @@ +// +// Test bench for the mipspipe +// Boram Lee +// + +`include "mipspipe.v" + +module test_mipspipe; + + reg clock; + reg [3:0] clock_cycle; + +// instantiate pipeline module + mipspipe u_mipspipe(clock); + +// initialize clock and cycle counter + initial begin + clock = 0; + clock_cycle=4'h0; + #160 $finish; + end + +// 10 unit clock cycle + always + #5 clock = ~clock; + + always @(posedge clock) + begin + clock_cycle=clock_cycle+1; + end + + +// display contents of pipeline latches at the end of each clock cycle + always @(negedge clock) + begin + $display("\n\nclock cycle = %d",clock_cycle," (time = %1.0t)",$time); + $display("IF/ID registers\n\t IF/ID.PC+4 = %h, IF/ID.IR = %h \n", u_mipspipe.PC, u_mipspipe.IFIDIR); + $display("ID/EX registers\n\t ID/EX.rs = %d, ID/EX.rt = %d",u_mipspipe.IDEXrs,u_mipspipe.IDEXrt,"\n\t ID/EX.A = %h, ID/EX.B = %h",u_mipspipe.IDEXA,u_mipspipe.IDEXB); + $display("\t ID/EX.op = %h\n",u_mipspipe.IDEXop); + $display("EX/MEM registers\n\t EX/MEM.rs = %d, EX/MEM.rt = %d",u_mipspipe.IDEXrs,u_mipspipe.IDEXrt,"\n\t EX/MEM.ALUOut = %h, EX/MEM.ALUout = %h",u_mipspipe.EXMEMALUOut,u_mipspipe.EXMEMB); + $display("\t EX/MEM.op = %h\n",u_mipspipe.EXMEMop); + $display("MEM/WB registers\n\t MEM/WB.rd = %d, MEM/WB.rt = %d",u_mipspipe.MEMWBrd,u_mipspipe.MEMWBrt,"\n\t MEM/WB.value = %h",u_mipspipe.MEMWBValue); + $display("\t EX/MEM.op = %h\n",u_mipspipe.MEMWBop); + end + +// log to a vcd (variable change dump) file + initial + begin + $dumpfile("test_mipspipe.vcd"); + $dumpvars; + end + +endmodule diff --git a/ee4363/mp1/mp12/test_mipspipe.vcd b/ee4363/mp1/mp12/test_mipspipe.vcd new file mode 100644 index 0000000..2cda5d0 --- /dev/null +++ b/ee4363/mp1/mp12/test_mipspipe.vcd @@ -0,0 +1,267 @@ +$date + Thu Dec 3 09:49:50 2020 +$end +$version + Icarus Verilog +$end +$timescale + 1s +$end +$scope module test_mipspipe $end +$var reg 1 ! clock $end +$var reg 4 " clock_cycle [3:0] $end +$scope module u_mipspipe $end +$var wire 32 # Ain [31:0] $end +$var wire 32 $ Bin [31:0] $end +$var wire 1 ! clock $end +$var wire 5 % MEMWBrt [4:0] $end +$var wire 5 & MEMWBrd [4:0] $end +$var wire 6 ' MEMWBop [5:0] $end +$var wire 5 ( IDEXrt [4:0] $end +$var wire 5 ) IDEXrs [4:0] $end +$var wire 6 * IDEXop [5:0] $end +$var wire 5 + EXMEMrd [4:0] $end +$var wire 6 , EXMEMop [5:0] $end +$var reg 32 - EXMEMALUOut [31:0] $end +$var reg 32 . EXMEMB [31:0] $end +$var reg 32 / EXMEMIR [31:0] $end +$var reg 32 0 IDEXA [31:0] $end +$var reg 32 1 IDEXB [31:0] $end +$var reg 32 2 IDEXIR [31:0] $end +$var reg 32 3 IFIDIR [31:0] $end +$var reg 32 4 MEMWBIR [31:0] $end +$var reg 32 5 MEMWBValue [31:0] $end +$var reg 32 6 PC [31:0] $end +$var reg 6 7 i [5:0] $end +$var reg 11 8 j [10:0] $end +$var reg 11 9 k [10:0] $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +b10000000000 9 +b10000000000 8 +b100000 7 +b0 6 +bx 5 +b100000 4 +b100000 3 +b100000 2 +bx 1 +bx 0 +b100000 / +bx . +bx - +b0 , +b0 + +b0 * +b0 ) +b0 ( +b0 ' +b0 & +b0 % +bx $ +bx # +b0 " +0! +$end +#5 +b0 $ +b0 1 +b0 # +b0 0 +b100 6 +b10000010010100000100000 3 +b1 " +1! +#10 +0! +#15 +b10 ) +b1 ( +b0 . +b0 - +b10000010010100000100000 2 +b1 $ +b1 1 +b10 # +b10 0 +b1000 6 +b10001100101000110000000000000100 3 +b10 " +1! +#20 +0! +#25 +b101 + +b101 ) +b11 ( +b100011 * +b0 5 +b1 . +b10000010010100000100000 / +b11 - +b10001100101000110000000000000100 2 +b11 $ +b11 1 +b101 # +b101 0 +b1100 6 +b10001100010000100000000000000000 3 +b11 " +1! +#30 +0! +#35 +b101 & +b1 % +b0 + +b100011 , +b10 ) +b10 ( +b10000010010100000100000 4 +b11 5 +b11 . +b10001100101000110000000000000100 / +b1001 - +b10001100010000100000000000000000 2 +b10 $ +b10 1 +b10 # +b10 0 +b10000 6 +b101000110001100000100101 3 +b100 " +1! +#40 +0! +#45 +b0 & +b11 % +b100011 ' +b101 ) +b11 ( +b0 * +b10001100101000110000000000000100 4 +b0 5 +b10 . +b10001100010000100000000000000000 / +b10 - +b101000110001100000100101 2 +b11 $ +b11 1 +b101 # +b101 0 +b10100 6 +b10101100101000110000000000000000 3 +b101 " +1! +#50 +0! +#55 +b10 % +b11 + +b0 , +b101011 * +b10001100010000100000000000000000 4 +b11 . +b101000110001100000100101 / +b111 - +b10101100101000110000000000000000 2 +b11 # +b11 0 +b11000 6 +b100000 3 +b110 " +1! +#60 +0! +#65 +b11 & +b11 % +b0 ' +b0 + +b101011 , +b0 ) +b0 ( +b0 * +b101000110001100000100101 4 +b111 5 +b10101100101000110000000000000000 / +b11 - +b100000 2 +b0 $ +b0 1 +b0 # +b0 0 +b11100 6 +b111 " +1! +#70 +0! +#75 +b0 & +b101011 ' +b0 , +b10101100101000110000000000000000 4 +b0 . +b100000 / +b0 - +b100000 6 +b1000 " +1! +#80 +0! +#85 +b0 % +b0 ' +b100000 4 +b0 5 +b100100 6 +b1001 " +1! +#90 +0! +#95 +b101000 6 +b1010 " +1! +#100 +0! +#105 +b101100 6 +b1011 " +1! +#110 +0! +#115 +b110000 6 +b1100 " +1! +#120 +0! +#125 +b110100 6 +b1101 " +1! +#130 +0! +#135 +b111000 6 +b1110 " +1! +#140 +0! +#145 +b111100 6 +b1111 " +1! +#150 +0! +#155 +b1000000 6 +b0 " +1! +#160 +0! diff --git a/ee4363/mp1/out b/ee4363/mp1/out deleted file mode 100644 index b57aa85..0000000 --- a/ee4363/mp1/out +++ /dev/null @@ -1,152 +0,0 @@ -#! /usr/bin/vvp -:ivl_version "10.3 (stable)"; -:ivl_delay_selection "TYPICAL"; -:vpi_time_precision - 10; -:vpi_module "system"; -:vpi_module "vhdl_sys"; -:vpi_module "v2005_math"; -:vpi_module "va_math"; -S_0x558b9129cd10 .scope module, "test_mipsalu" "test_mipsalu" 2 8; - .timescale -9 -10; -v0x558b912b2050_0 .var "A", 31 0; -v0x558b912b2130_0 .net "ALUOut", 31 0, v0x558b912b1b10_0; 1 drivers -v0x558b912b2200_0 .var "ALUctl", 3 0; -v0x558b912b2300_0 .var "B", 31 0; -v0x558b912b23d0_0 .net "Zero", 0 0, L_0x558b912c2530; 1 drivers -S_0x558b9129ce90 .scope module, "U0" "MIPSALU" 2 19, 3 1 0, S_0x558b9129cd10; - .timescale -9 -10; - .port_info 0 /INPUT 4 "ALUctl" - .port_info 1 /INPUT 32 "A" - .port_info 2 /INPUT 32 "B" - .port_info 3 /OUTPUT 32 "ALUOut" - .port_info 4 /OUTPUT 1 "Zero" -v0x558b91265130_0 .net "A", 31 0, v0x558b912b2050_0; 1 drivers -v0x558b912b1b10_0 .var "ALUOut", 31 0; -v0x558b912b1bf0_0 .net "ALUctl", 3 0, v0x558b912b2200_0; 1 drivers -v0x558b912b1ce0_0 .net "B", 31 0, v0x558b912b2300_0; 1 drivers -v0x558b912b1dc0_0 .net "Zero", 0 0, L_0x558b912c2530; alias, 1 drivers -L_0x7f2d75820018 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x558b912b1ed0_0 .net/2u *"_s0", 31 0, L_0x7f2d75820018; 1 drivers -E_0x558b9129a7b0 .event edge, v0x558b912b1ce0_0, v0x558b91265130_0, v0x558b912b1bf0_0; -L_0x558b912c2530 .cmp/eq 32, v0x558b912b1b10_0, L_0x7f2d75820018; - .scope S_0x558b9129ce90; -T_0 ; - %wait E_0x558b9129a7b0; - %load/vec4 v0x558b912b1bf0_0; - %dup/vec4; - %pushi/vec4 0, 0, 4; - %cmp/u; - %jmp/1 T_0.0, 6; - %dup/vec4; - %pushi/vec4 1, 0, 4; - %cmp/u; - %jmp/1 T_0.1, 6; - %dup/vec4; - %pushi/vec4 2, 0, 4; - %cmp/u; - %jmp/1 T_0.2, 6; - %dup/vec4; - %pushi/vec4 6, 0, 4; - %cmp/u; - %jmp/1 T_0.3, 6; - %dup/vec4; - %pushi/vec4 7, 0, 4; - %cmp/u; - %jmp/1 T_0.4, 6; - %dup/vec4; - %pushi/vec4 12, 0, 4; - %cmp/u; - %jmp/1 T_0.5, 6; - %pushi/vec4 0, 0, 32; - %assign/vec4 v0x558b912b1b10_0, 0; - %jmp T_0.7; -T_0.0 ; - %load/vec4 v0x558b91265130_0; - %load/vec4 v0x558b912b1ce0_0; - %and; - %assign/vec4 v0x558b912b1b10_0, 0; - %jmp T_0.7; -T_0.1 ; - %load/vec4 v0x558b91265130_0; - %load/vec4 v0x558b912b1ce0_0; - %or; - %assign/vec4 v0x558b912b1b10_0, 0; - %jmp T_0.7; -T_0.2 ; - %load/vec4 v0x558b91265130_0; - %load/vec4 v0x558b912b1ce0_0; - %add; - %assign/vec4 v0x558b912b1b10_0, 0; - %jmp T_0.7; -T_0.3 ; - %load/vec4 v0x558b91265130_0; - %load/vec4 v0x558b912b1ce0_0; - %sub; - %assign/vec4 v0x558b912b1b10_0, 0; - %jmp T_0.7; -T_0.4 ; - %load/vec4 v0x558b91265130_0; - %load/vec4 v0x558b912b1ce0_0; - %cmp/u; - %flag_mov 8, 5; - %jmp/0 T_0.8, 8; - %pushi/vec4 1, 0, 32; - %jmp/1 T_0.9, 8; -T_0.8 ; End of true expr. - %pushi/vec4 0, 0, 32; - %jmp/0 T_0.9, 8; - ; End of false expr. - %blend; -T_0.9; - %assign/vec4 v0x558b912b1b10_0, 0; - %jmp T_0.7; -T_0.5 ; - %load/vec4 v0x558b91265130_0; - %load/vec4 v0x558b912b1ce0_0; - %or; - %inv; - %assign/vec4 v0x558b912b1b10_0, 0; - %jmp T_0.7; -T_0.7 ; - %pop/vec4 1; - %jmp T_0; - .thread T_0, $push; - .scope S_0x558b9129cd10; -T_1 ; - %pushi/vec4 1431655765, 0, 32; - %store/vec4 v0x558b912b2050_0, 0, 32; - %pushi/vec4 1431655765, 0, 32; - %store/vec4 v0x558b912b2300_0, 0, 32; - %delay 100, 0; - %pushi/vec4 0, 0, 4; - %store/vec4 v0x558b912b2200_0, 0, 4; - %delay 100, 0; - %pushi/vec4 1, 0, 4; - %store/vec4 v0x558b912b2200_0, 0, 4; - %delay 100, 0; - %pushi/vec4 2, 0, 4; - %store/vec4 v0x558b912b2200_0, 0, 4; - %delay 100, 0; - %pushi/vec4 6, 0, 4; - %store/vec4 v0x558b912b2200_0, 0, 4; - %delay 100, 0; - %vpi_call 2 32 "$finish" {0 0 0}; - %end; - .thread T_1; - .scope S_0x558b9129cd10; -T_2 ; - %vpi_call 2 38 "$monitor", $time, " A = %h", v0x558b912b2050_0, " B = %h", v0x558b912b2300_0, " ALUOut = %h", v0x558b912b2130_0, " Zero = %b", v0x558b912b23d0_0 {0 0 0}; - %end; - .thread T_2; - .scope S_0x558b9129cd10; -T_3 ; - %vpi_call 2 43 "$dumpfile", "MIPSAlu.vcd" {0 0 0}; - %vpi_call 2 44 "$dumpvars" {0 0 0}; - %end; - .thread T_3; -# The file index is used to find the file name in the following table. -:file_names 4; - "N/A"; - ""; - "test_mipsalu.v"; - "./MIPSALU.v"; diff --git a/ee4363/mp1/test_mipsalu.v b/ee4363/mp1/test_mipsalu.v deleted file mode 100644 index 15cdf60..0000000 --- a/ee4363/mp1/test_mipsalu.v +++ /dev/null @@ -1,49 +0,0 @@ - `timescale 1ns/100ps -// -// Test Bench for the mips alu -// T. Posbergh, 14 October 2012 -// - `include "MIPSALU.v" -// -module test_mipsalu; - wire Zero; // ALU bit output - wire [31:0] ALUOut; // ALU word output - reg [31:0] A,B; // ALU word inpus - reg [3:0] ALUctl; - - reg clock; - reg reset; - -// instantiate the alu and control - - MIPSALU U0(ALUctl, A, B, ALUOut, Zero); - -// generate test signals - - initial - begin - A=32'b0101_0101_0101_0101_0101_0101_0101_0101; - B=32'b0101_0101_0101_0101_0101_0101_0101_0101; - #10 ALUctl=4'b0000; - #10 ALUctl=4'b0001; - #10 ALUctl=4'b0010; - #10 ALUctl=4'b0110; -// $finish(100); - #10 $finish; - end - -// output result - - initial - $monitor($time, " A = %h",A," B = %h",B," ALUOut = %h",ALUOut," Zero = %b",Zero); - -// the following generates vcd file for GTKwave - initial - begin - $dumpfile("MIPSAlu.vcd"); - $dumpvars; - end - -endmodule - - diff --git a/ee4363/mp1/test_mipspipe.v b/ee4363/mp1/test_mipspipe.v deleted file mode 100644 index 24576ec..0000000 --- a/ee4363/mp1/test_mipspipe.v +++ /dev/null @@ -1,53 +0,0 @@ -// -// Test bench for the mipspipe -// Boram Lee -// - -`include "mipspipe.v" - -module test_mipspipe; - - reg clock; - reg [3:0] clock_cycle; - -// instantiate pipeline module - mipspipe u_mipspipe(clock); - -// initialize clock and cycle counter - initial begin - clock = 0; - clock_cycle=4'h0; - #160 $finish; - end - -// 10 unit clock cycle - always - #5 clock = ~clock; - - always @(posedge clock) - begin - clock_cycle=clock_cycle+1; - end - - -// display contents of pipeline latches at the end of each clock cycle - always @(negedge clock) - begin - $display("\n\nclock cycle = %d",clock_cycle," (time = %1.0t)",$time); - $display("IF/ID registers\n\t IF/ID.PC+4 = %h, IF/ID.IR = %h \n", u_mipspipe.PC, u_mipspipe.IFIDIR); - $display("ID/EX registers\n\t ID/EX.rs = %d, ID/EX.rt = %d",u_mipspipe.IDEXrs,u_mipspipe.IDEXrt,"\n\t ID/EX.A = %h, ID/EX.B = %h",u_mipspipe.IDEXA,u_mipspipe.IDEXB); - $display("\t ID/EX.op = %h\n",u_mipspipe.IDEXop); - $display("EX/MEM registers\n\t EX/MEM.rs = %d, EX/MEM.rt = %d",u_mipspipe.IDEXrs,u_mipspipe.IDEXrt,"\n\t EX/MEM.ALUOut = %h, EX/MEM.ALUout = %h",u_mipspipe.EXMEMALUOut,u_mipspipe.EXMEMB); - $display("\t EX/MEM.op = %h\n",u_mipspipe.EXMEMop); - $display("MEM/WB registers\n\t MEM/WB.rd = %d, MEM/WB.rt = %d",u_mipspipe.MEMWBrd,u_mipspipe.MEMWBrt,"\n\t MEM/WB.value = %h",u_mipspipe.MEMWBValue); - $display("\t EX/MEM.op = %h\n",u_mipspipe.MEMWBop); - end - -// log to a vcd (variable change dump) file - initial - begin - $dumpfile("test_mipspipe.vcd"); - $dumpvars; - end - -endmodule -- cgit v1.2.3