From 03e522d164dfd9e49a1fbc2f23134cdcb1544286 Mon Sep 17 00:00:00 2001 From: RossTheRoss Date: Fri, 18 Dec 2020 19:42:33 -0600 Subject: comment --- ee4363/mp2/mipspipe_mp2.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'ee4363/mp2/mipspipe_mp2.v') diff --git a/ee4363/mp2/mipspipe_mp2.v b/ee4363/mp2/mipspipe_mp2.v index 784b669..9ea9fc2 100644 --- a/ee4363/mp2/mipspipe_mp2.v +++ b/ee4363/mp2/mipspipe_mp2.v @@ -43,7 +43,7 @@ module mipspipe_mp2 (clock); assign bypassAfromLWinWB = (IDEXrs == MEMWBIR[20:16]) & (IDEXrs!=0) & (MEMWBop==LW); // The bypass to input B from the WB stage for an LW operation assign bypassBfromLWinWB = 0; - //Stall in case of WB + //Stall to bypass A or B if need b (I'm not sorry) assign bypassIDEXAfromWB = ((MEMWBIR != nop) & (IFIDIR != nop) & (IFIDrs == MEMWBrt) & (MEMWBop == LW)) | ((MEMWBop == ALUop) & (MEMWBrd == IFIDrs)); assign bypassIDEXBfromWB = ((MEMWBIR != nop) & (IFIDIR != nop) & (IFIDrt == MEMWBrt) & (MEMWBop == LW)) | -- cgit v1.2.3