From 7a73162607544204032aa66cce755daf21edebda Mon Sep 17 00:00:00 2001 From: Matt Strapp Date: Tue, 24 May 2022 11:18:46 -0500 Subject: Graduate Signed-off-by: Matt Strapp --- ee4363/mp2/mipspipe_mp2.v | 159 +++++++++++ ee4363/mp2/out | 580 +++++++++++++++++++++++++++++++++++++++++ ee4363/mp2/output.txt | 319 +++++++++++++++++++++++ ee4363/mp2/test_mipspipe.vcd | 413 +++++++++++++++++++++++++++++ ee4363/mp2/test_mipspipe_mp2.v | 53 ++++ 5 files changed, 1524 insertions(+) create mode 100644 ee4363/mp2/mipspipe_mp2.v create mode 100644 ee4363/mp2/out create mode 100644 ee4363/mp2/output.txt create mode 100644 ee4363/mp2/test_mipspipe.vcd create mode 100644 ee4363/mp2/test_mipspipe_mp2.v (limited to 'ee4363/mp2') diff --git a/ee4363/mp2/mipspipe_mp2.v b/ee4363/mp2/mipspipe_mp2.v new file mode 100644 index 0000000..9ea9fc2 --- /dev/null +++ b/ee4363/mp2/mipspipe_mp2.v @@ -0,0 +1,159 @@ +// Incomplete behavioral model of MIPS pipeline + +module mipspipe_mp2 (clock); + // in_out + input clock; + + // Instruction opcodes + parameter LW = 6'b100011, SW = 6'b101011, BEQ = 6'b000100, nop = 32'b00000_100000, ALUop = 6'b0; + reg [31:0] PC, Regs[0:31], IMemory[0:1023], DMemory[0:1023], // instruction and data memories + IFIDIR, IDEXA, IDEXB, IDEXIR, EXMEMIR, EXMEMB, // pipeline latches + EXMEMALUOut, MEMWBValue, MEMWBIR; + + wire [4:0] IDEXrs, IDEXrt, EXMEMrd, MEMWBrd, MEMWBrt, IFIDrt, IFIDrs; // hold register fields + wire [5:0] EXMEMop, MEMWBop, IDEXop, IFIDop; // hold opcodes + wire [31:0] Ain, Bin; // ALU inputs + + // declare the bypass signals + wire bypassAfromMEM, bypassAfromALUinWB, bypassBfromMEM, bypassBfromALUinWB, bypassAfromLWinWB, bypassBfromLWinWB, bypassIDEXAfromWB, bypassIDEXBfromWB, STALL; + + // Define fields of pipeline latches + assign IDEXrs = IDEXIR[25:21]; // rs field + assign IDEXrt = IDEXIR[20:16]; // rt field + assign EXMEMrd = EXMEMIR[15:11]; // rd field + assign MEMWBrd = MEMWBIR[15:11]; // rd field + assign MEMWBrt = MEMWBIR[20:16]; // rt field -- for loads + assign EXMEMop = EXMEMIR[31:26]; // opcode + assign MEMWBop = MEMWBIR[31:26]; // opcode + assign IDEXop = IDEXIR[31:26]; // opcode + assign IFIDrs = IFIDIR[25:21]; + assign IFIDrt = IFIDIR[20:16]; + assign IFIDop = IFIDIR[31:26]; + + + // The bypass to input A from the MEM stage for an ALU operation + assign bypassAfromMEM = (IDEXrs == EXMEMrd) & (IDEXrs!=0) & (EXMEMop==ALUop); + // The bypass to input B from the MEM stage for an ALU operation + assign bypassBfromMEM = 0; + // The bypass to input A from the WB stage for an ALU operation + assign bypassAfromALUinWB = 0; + // The bypass to input B from the WB stage for an ALU operation + assign bypassBfromALUinWB = 0; + // The bypass to input A from the WB stage for an LW operation + assign bypassAfromLWinWB = (IDEXrs == MEMWBIR[20:16]) & (IDEXrs!=0) & (MEMWBop==LW); + // The bypass to input B from the WB stage for an LW operation + assign bypassBfromLWinWB = 0; + //Stall to bypass A or B if need b (I'm not sorry) + assign bypassIDEXAfromWB = ((MEMWBIR != nop) & (IFIDIR != nop) & (IFIDrs == MEMWBrt) & (MEMWBop == LW)) | + ((MEMWBop == ALUop) & (MEMWBrd == IFIDrs)); + assign bypassIDEXBfromWB = ((MEMWBIR != nop) & (IFIDIR != nop) & (IFIDrt == MEMWBrt) & (MEMWBop == LW)) | + ((MEMWBop == ALUop) & (MEMWBrd == IFIDrt)); + // The A input to the ALU is bypassed from MEM if there is a bypass there, + // Otherwise from WB if there is a bypass there, and otherwise comes from the IDEX register + assign Ain = bypassAfromMEM? EXMEMALUOut : (bypassAfromALUinWB | bypassAfromLWinWB)? MEMWBValue : IDEXA; + + // The B input to the ALU is bypassed from MEM if there is a bypass there, + // Otherwise from WB if there is a bypass there, and otherwise comes from the IDEX register + // Ripped off of above just replacing "A" with "B" + assign Bin = bypassBfromMEM? EXMEMALUOut : (bypassBfromALUinWB | bypassBfromLWinWB)? MEMWBValue : IDEXB; + + + reg [5:0] i; // used to initialize latches + reg [10:0] j,k; // used to initialize memories + + // Make the Big Stall + assign STALL = (IDEXop == LW) && + //All of this is anded with the above (Lisp would be proud) + (((IFIDop == LW) && (IFIDrs == IDEXrt)) | + ((IFIDop == ALUop) && ((IFIDrs == IDEXrt) | (IFIDrt == IDEXrt))) | + ((IFIDop == SW) && ((IFIDrs == IDEXrt) | (IFIDrt == IDEXrt)))); + + initial begin + PC = 0; + IFIDIR = nop; + IDEXIR = nop; + EXMEMIR = nop; + MEMWBIR = nop; // no-ops in pipeline latches + + for (i = 0;i<=31;i = i+1) Regs[i] = i; // initialize latches + + IMemory[0] = 32'h00412820; // ADD $5, $2, $1 + IMemory[1] = 32'h8ca30004; // LW $3, 4($5) + IMemory[2] = 32'haca70005; // SW $7, 5($5) + // Hazard 1: ADD might not have written to $5 before SW reads from $5 (Type 2: Read after Write) + IMemory[3] = 32'h00602020; // ADD $4, $3, $0 + // Hazard 2: ADD might read $3 before LW writes to $3 (Type 3: Write after read) + IMemory[4] = 32'h01093020; // ADD $6, $8, $9 + IMemory[5] = 32'hac06000c; // SW $6, $12($0) + // Hazard 3: ADD and SW are trying to access the same register (Type 1: Write after Write) + IMemory[6] = 32'h00c05020; // ADD $10, $6, $0 + // Hazard 4: ADD reads from $6 and is written to (twice) immediately beforehand (Type 2: Read after Write) + IMemory[7] = 32'h8c0b0010; // LW $11, 32($0) + IMemory[8] = 32'h00000020; // ADD $0, $0, $0 + IMemory[9] = 32'h002b6020; // ADD $12, $1, $11 + // Hazard 5: LW might not have written to $11 before the last ADD reads from $11 (Type 2: Read after Write) + for (j=10; j<=1023; j=j+1) IMemory[j] = nop; + + DMemory[0] = 32'h00000000; + DMemory[1] = 32'hffffffff; + DMemory[2] = 32'h00000000; + DMemory[3] = 32'h00000000; + DMemory[4] = 32'hfffffffe; + for (k=5; k<=1023; k=k+1) DMemory[k] = 0; + end + + always @ (posedge clock) begin + if (~STALL) begin + // FETCH: Fetch instruction & update PC + IFIDIR <= IMemory[PC>>2]; + PC <= PC + 4; + + // DECODE: Read registers + if (~bypassIDEXAfromWB) begin + IDEXA <= Regs[IFIDIR[25:21]]; + end + else begin + IDEXA <= MEMWBValue; + end + + if (~bypassIDEXBfromWB) begin + IDEXB <= Regs[IFIDIR[20:16]]; + end + else begin + IDEXB <= MEMWBValue; + end + IDEXIR <= IFIDIR; + end + else begin //IF (STALL) + IDEXIR <= nop; + end + + // EX: Address calculation or ALU operation + if ((IDEXop==LW) |(IDEXop==SW)) // address calculation & copy B + EXMEMALUOut <= Ain +{{16{IDEXIR[15]}}, IDEXIR[15:0]}; + else if (IDEXop==ALUop) begin + case (IDEXIR[5:0]) // R-type instruction + 32: EXMEMALUOut <= Ain + Bin; // add operation + default: ; // other R-type operations: subtract, SLT, etc. + endcase + end + + EXMEMIR <= IDEXIR; + EXMEMB <= Bin; // pass along the IR & B register + + // MEM + if (EXMEMop==ALUop) MEMWBValue <= EXMEMALUOut; // pass along ALU result + else if (EXMEMop == LW) MEMWBValue <= DMemory[EXMEMALUOut>>2]; + else if (EXMEMop == SW) DMemory[EXMEMALUOut>>2] <=EXMEMB; // store + + MEMWBIR <= EXMEMIR; // pass along IR + + // WB + if ((MEMWBop==ALUop) & (MEMWBrd != 0)) // update latches if ALU operation and destination not 0 + Regs[MEMWBrd] <= MEMWBValue; // ALU operation + else if ((MEMWBop == LW)& (MEMWBrt != 0)) // Update latches if load and destination not 0 + Regs[MEMWBrt] <= MEMWBValue; + end + +endmodule + diff --git a/ee4363/mp2/out b/ee4363/mp2/out new file mode 100644 index 0000000..689fc48 --- /dev/null +++ b/ee4363/mp2/out @@ -0,0 +1,580 @@ +#! /usr/bin/vvp +:ivl_version "10.3 (stable)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision + 0; +:vpi_module "system"; +:vpi_module "vhdl_sys"; +:vpi_module "v2005_math"; +:vpi_module "va_math"; +S_0x5566537b5770 .scope module, "test_mipspipe" "test_mipspipe" 2 8; + .timescale 0 0; +v0x5566537e7d40_0 .var "clock", 0 0; +v0x5566537e7de0_0 .var "clock_cycle", 3 0; +E_0x55665379cec0 .event negedge, v0x5566537e79a0_0; +S_0x556653785590 .scope module, "u_mipspipe_mp2" "mipspipe_mp2" 2 14, 3 3 0, S_0x5566537b5770; + .timescale 0 0; + .port_info 0 /INPUT 1 "clock" +P_0x55665378c9c0 .param/l "ALUop" 0 3 8, C4<000000>; +P_0x55665378ca00 .param/l "BEQ" 0 3 8, C4<000100>; +P_0x55665378ca40 .param/l "LW" 0 3 8, C4<100011>; +P_0x55665378ca80 .param/l "SW" 0 3 8, C4<101011>; +P_0x55665378cac0 .param/l "nop" 0 3 8, C4<00000000000000000000000000100000>; +L_0x5566537934c0 .functor AND 1, L_0x5566537e88e0, L_0x5566537f8ba0, C4<1>, C4<1>; +L_0x55665375ea40 .functor AND 1, L_0x5566537934c0, L_0x5566537f8e30, C4<1>, C4<1>; +L_0x55665375e820 .functor AND 1, L_0x5566537f9190, L_0x5566537f93d0, C4<1>, C4<1>; +L_0x55665375e930 .functor AND 1, L_0x55665375e820, L_0x5566537f95e0, C4<1>, C4<1>; +L_0x5566537933f0 .functor AND 1, L_0x5566537f9330, L_0x5566537f98a0, C4<1>, C4<1>; +L_0x5566537bfe70 .functor AND 1, L_0x5566537933f0, L_0x5566537f9b30, C4<1>, C4<1>; +L_0x5566537bfee0 .functor AND 1, L_0x5566537bfe70, L_0x5566537f9d50, C4<1>, C4<1>; +L_0x5566537e8a00 .functor AND 1, L_0x5566537f9fb0, L_0x5566537fa0e0, C4<1>, C4<1>; +L_0x5566537fa3a0 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*"_s174", 0 0, L_0x5566537fcc60; 1 drivers +v0x5566537e5370_0 .net *"_s176", 0 0, L_0x5566537fcd70; 1 drivers +v0x5566537e5430_0 .net *"_s178", 0 0, L_0x5566537fcf40; 1 drivers +v0x5566537e5510_0 .net *"_s22", 0 0, L_0x5566537e88e0; 1 drivers +v0x5566537e59e0_0 .net *"_s24", 31 0, L_0x5566537e8a70; 1 drivers +L_0x7fd2876a2018 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x5566537e5ac0_0 .net *"_s27", 26 0, L_0x7fd2876a2018; 1 drivers +L_0x7fd2876a2060 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x5566537e5ba0_0 .net/2u *"_s28", 31 0, L_0x7fd2876a2060; 1 drivers +v0x5566537e5c80_0 .net *"_s30", 0 0, L_0x5566537f8ba0; 1 drivers +v0x5566537e5d40_0 .net *"_s32", 0 0, L_0x5566537934c0; 1 drivers +L_0x7fd2876a20a8 .functor BUFT 1, C4<000000>, C4<0>, C4<0>, C4<0>; +v0x5566537e5e20_0 .net/2u *"_s34", 5 0, L_0x7fd2876a20a8; 1 drivers +v0x5566537e5f00_0 .net *"_s36", 0 0, L_0x5566537f8e30; 1 drivers +v0x5566537e5fc0_0 .net *"_s47", 4 0, L_0x5566537f9060; 1 drivers +v0x5566537e60a0_0 .net *"_s48", 0 0, L_0x5566537f9190; 1 drivers +v0x5566537e6160_0 .net *"_s50", 31 0, L_0x5566537f9260; 1 drivers +L_0x7fd2876a21c8 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x5566537e6240_0 .net *"_s53", 26 0, L_0x7fd2876a21c8; 1 drivers +L_0x7fd2876a2210 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x5566537e6320_0 .net/2u *"_s54", 31 0, L_0x7fd2876a2210; 1 drivers +v0x5566537e6400_0 .net *"_s56", 0 0, L_0x5566537f93d0; 1 drivers +v0x5566537e64c0_0 .net *"_s58", 0 0, L_0x55665375e820; 1 drivers +L_0x7fd2876a2258 .functor BUFT 1, C4<100011>, C4<0>, C4<0>, C4<0>; +v0x5566537e65a0_0 .net/2u *"_s60", 5 0, L_0x7fd2876a2258; 1 drivers +v0x5566537e6680_0 .net *"_s62", 0 0, L_0x5566537f95e0; 1 drivers +L_0x7fd2876a22e8 .functor BUFT 1, C4<00000000000000000000000000100000>, C4<0>, C4<0>, C4<0>; +v0x5566537e6740_0 .net/2u *"_s68", 31 0, L_0x7fd2876a22e8; 1 drivers +v0x5566537e6820_0 .net *"_s70", 0 0, L_0x5566537f9330; 1 drivers +L_0x7fd2876a2330 .functor BUFT 1, C4<00000000000000000000000000100000>, C4<0>, C4<0>, C4<0>; +v0x5566537e68e0_0 .net/2u *"_s72", 31 0, L_0x7fd2876a2330; 1 drivers +v0x5566537e69c0_0 .net *"_s74", 0 0, L_0x5566537f98a0; 1 drivers +v0x5566537e6a80_0 .net *"_s76", 0 0, L_0x5566537933f0; 1 drivers +v0x5566537e6b60_0 .net *"_s78", 0 0, L_0x5566537f9b30; 1 drivers +v0x5566537e6c20_0 .net *"_s80", 0 0, L_0x5566537bfe70; 1 drivers +L_0x7fd2876a2378 .functor BUFT 1, C4<100011>, C4<0>, C4<0>, C4<0>; +v0x5566537e6d00_0 .net/2u *"_s82", 5 0, L_0x7fd2876a2378; 1 drivers +v0x5566537e6de0_0 .net *"_s84", 0 0, L_0x5566537f9d50; 1 drivers +v0x5566537e6ea0_0 .net *"_s86", 0 0, L_0x5566537bfee0; 1 drivers +L_0x7fd2876a23c0 .functor BUFT 1, C4<000000>, C4<0>, C4<0>, C4<0>; +v0x5566537e6f80_0 .net/2u *"_s88", 5 0, L_0x7fd2876a23c0; 1 drivers +v0x5566537e7060_0 .net *"_s90", 0 0, L_0x5566537f9fb0; 1 drivers +v0x5566537e7120_0 .net *"_s92", 0 0, L_0x5566537fa0e0; 1 drivers +v0x5566537e71e0_0 .net *"_s94", 0 0, L_0x5566537e8a00; 1 drivers +L_0x7fd2876a2408 .functor BUFT 1, C4<00000000000000000000000000100000>, C4<0>, C4<0>, C4<0>; +v0x5566537e72c0_0 .net/2u *"_s98", 31 0, L_0x7fd2876a2408; 1 drivers +v0x5566537e73a0_0 .net "bypassAfromALUinWB", 0 0, L_0x7fd2876a2138; 1 drivers +v0x5566537e7460_0 .net "bypassAfromLWinWB", 0 0, L_0x55665375e930; 1 drivers +v0x5566537e7520_0 .net "bypassAfromMEM", 0 0, L_0x55665375ea40; 1 drivers +v0x5566537e75e0_0 .net "bypassBfromALUinWB", 0 0, L_0x7fd2876a2180; 1 drivers +v0x5566537e76a0_0 .net "bypassBfromLWinWB", 0 0, L_0x7fd2876a22a0; 1 drivers +L_0x7fd2876a20f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x5566537e7760_0 .net "bypassBfromMEM", 0 0, L_0x7fd2876a20f0; 1 drivers +v0x5566537e7820_0 .net "bypassIDEXAfromWB", 0 0, L_0x5566537fa3a0; 1 drivers +v0x5566537e78e0_0 .net "bypassIDEXBfromWB", 0 0, L_0x5566537fb1c0; 1 drivers +v0x5566537e79a0_0 .net "clock", 0 0, v0x5566537e7d40_0; 1 drivers +v0x5566537e7a60_0 .var "i", 5 0; +v0x5566537e7b40_0 .var "j", 10 0; +v0x5566537e7c20_0 .var "k", 10 0; +E_0x55665379d1b0 .event posedge, v0x5566537e79a0_0; +L_0x5566537e7ea0 .part v0x5566537e2870_0, 21, 5; +L_0x5566537e7f40 .part v0x5566537e2870_0, 16, 5; +L_0x5566537e7fe0 .part v0x5566537e2410_0, 11, 5; +L_0x5566537e80b0 .part v0x5566537e3030_0, 11, 5; +L_0x5566537e81e0 .part v0x5566537e3030_0, 16, 5; +L_0x5566537e8300 .part v0x5566537e2410_0, 26, 6; +L_0x5566537e8430 .part v0x5566537e3030_0, 26, 6; +L_0x5566537e84d0 .part v0x5566537e2870_0, 26, 6; +L_0x5566537e85c0 .part v0x5566537e2bf0_0, 21, 5; +L_0x5566537e86c0 .part v0x5566537e2bf0_0, 16, 5; +L_0x5566537e8840 .part v0x5566537e2bf0_0, 26, 6; +L_0x5566537e88e0 .cmp/eq 5, L_0x5566537e7ea0, L_0x5566537e7fe0; +L_0x5566537e8a70 .concat [ 5 27 0 0], L_0x5566537e7ea0, L_0x7fd2876a2018; +L_0x5566537f8ba0 .cmp/ne 32, L_0x5566537e8a70, L_0x7fd2876a2060; +L_0x5566537f8e30 .cmp/eq 6, L_0x5566537e8300, L_0x7fd2876a20a8; +L_0x5566537f9060 .part v0x5566537e3030_0, 16, 5; +L_0x5566537f9190 .cmp/eq 5, L_0x5566537e7ea0, L_0x5566537f9060; +L_0x5566537f9260 .concat [ 5 27 0 0], L_0x5566537e7ea0, L_0x7fd2876a21c8; +L_0x5566537f93d0 .cmp/ne 32, L_0x5566537f9260, L_0x7fd2876a2210; +L_0x5566537f95e0 .cmp/eq 6, L_0x5566537e8430, L_0x7fd2876a2258; +L_0x5566537f9330 .cmp/ne 32, v0x5566537e3030_0, L_0x7fd2876a22e8; +L_0x5566537f98a0 .cmp/ne 32, v0x5566537e2bf0_0, L_0x7fd2876a2330; +L_0x5566537f9b30 .cmp/eq 5, L_0x5566537e85c0, L_0x5566537e81e0; +L_0x5566537f9d50 .cmp/eq 6, L_0x5566537e8430, L_0x7fd2876a2378; +L_0x5566537f9fb0 .cmp/eq 6, L_0x5566537e8430, L_0x7fd2876a23c0; +L_0x5566537fa0e0 .cmp/eq 5, L_0x5566537e80b0, L_0x5566537e85c0; +L_0x5566537fa4b0 .cmp/ne 32, v0x5566537e3030_0, L_0x7fd2876a2408; +L_0x5566537fa5a0 .cmp/ne 32, v0x5566537e2bf0_0, L_0x7fd2876a2450; +L_0x5566537fa8f0 .cmp/eq 5, L_0x5566537e86c0, L_0x5566537e81e0; +L_0x5566537faaa0 .cmp/eq 6, L_0x5566537e8430, L_0x7fd2876a2498; +L_0x5566537fae10 .cmp/eq 6, L_0x5566537e8430, L_0x7fd2876a24e0; +L_0x5566537faf00 .cmp/eq 5, L_0x5566537e80b0, L_0x5566537e86c0; +L_0x5566537fb3f0 .functor MUXZ 32, v0x5566537e26b0_0, v0x5566537e3110_0, L_0x5566537fada0, C4<>; +L_0x5566537fb4e0 .functor MUXZ 32, L_0x5566537fb3f0, v0x5566537e2200_0, L_0x55665375ea40, C4<>; +L_0x5566537fb8e0 .functor MUXZ 32, v0x5566537e2790_0, v0x5566537e3110_0, L_0x5566537fb740, C4<>; +L_0x5566537fba20 .cmp/eq 6, L_0x5566537e84d0, L_0x7fd2876a2528; +L_0x5566537fb580 .cmp/eq 6, L_0x5566537e8840, L_0x7fd2876a2570; +L_0x5566537fbce0 .cmp/eq 5, L_0x5566537e85c0, L_0x5566537e7f40; +L_0x5566537fbfd0 .cmp/eq 6, L_0x5566537e8840, L_0x7fd2876a25b8; +L_0x5566537fc0c0 .cmp/eq 5, L_0x5566537e85c0, L_0x5566537e7f40; +L_0x5566537fc2b0 .cmp/eq 5, L_0x5566537e86c0, L_0x5566537e7f40; +L_0x5566537fc4e0 .cmp/eq 6, L_0x5566537e8840, L_0x7fd2876a2600; +L_0x5566537fc9b0 .cmp/eq 5, L_0x5566537e85c0, L_0x5566537e7f40; +L_0x5566537fca50 .cmp/eq 5, L_0x5566537e86c0, L_0x5566537e7f40; + .scope S_0x556653785590; +T_0 ; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x5566537e3490_0, 0, 32; + %pushi/vec4 32, 0, 32; + %store/vec4 v0x5566537e2bf0_0, 0, 32; + %pushi/vec4 32, 0, 32; + %store/vec4 v0x5566537e2870_0, 0, 32; + %pushi/vec4 32, 0, 32; + %store/vec4 v0x5566537e2410_0, 0, 32; + %pushi/vec4 32, 0, 32; + %store/vec4 v0x5566537e3030_0, 0, 32; + %pushi/vec4 0, 0, 6; + %store/vec4 v0x5566537e7a60_0, 0, 6; +T_0.0 ; + %load/vec4 v0x5566537e7a60_0; + %pad/u 32; + %cmpi/u 31, 0, 32; + %flag_or 5, 4; + %jmp/0xz T_0.1, 5; + %load/vec4 v0x5566537e7a60_0; + %pad/u 32; + %load/vec4 v0x5566537e7a60_0; + %pad/u 7; + %ix/vec4 4; + %store/vec4a v0x5566537e3570, 4, 0; + %load/vec4 v0x5566537e7a60_0; + %addi 1, 0, 6; + %store/vec4 v0x5566537e7a60_0, 0, 6; + %jmp T_0.0; +T_0.1 ; + %pushi/vec4 4270112, 0, 32; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x5566537e2f70, 4, 0; + %pushi/vec4 2359492612, 0, 32; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x5566537e2f70, 4, 0; + %pushi/vec4 2896625669, 0, 32; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x5566537e2f70, 4, 0; + %pushi/vec4 6299680, 0, 32; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x5566537e2f70, 4, 0; + %pushi/vec4 17379360, 0, 32; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x5566537e2f70, 4, 0; + %pushi/vec4 2886074380, 0, 32; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x5566537e2f70, 4, 0; + %pushi/vec4 12603424, 0, 32; + %ix/load 4, 6, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x5566537e2f70, 4, 0; + %pushi/vec4 2349531152, 0, 32; + %ix/load 4, 7, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x5566537e2f70, 4, 0; + %pushi/vec4 32, 0, 32; + %ix/load 4, 8, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x5566537e2f70, 4, 0; + %pushi/vec4 2842656, 0, 32; + %ix/load 4, 9, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x5566537e2f70, 4, 0; + %pushi/vec4 10, 0, 11; + %store/vec4 v0x5566537e7b40_0, 0, 11; +T_0.2 ; + %load/vec4 v0x5566537e7b40_0; + %pad/u 32; + %cmpi/u 1023, 0, 32; + %flag_or 5, 4; + %jmp/0xz T_0.3, 5; + %pushi/vec4 32, 0, 32; + %load/vec4 v0x5566537e7b40_0; + %pad/u 12; + %ix/vec4 4; + %store/vec4a v0x5566537e2f70, 4, 0; + %load/vec4 v0x5566537e7b40_0; + %addi 1, 0, 11; + %store/vec4 v0x5566537e7b40_0, 0, 11; + %jmp T_0.2; +T_0.3 ; + %pushi/vec4 0, 0, 32; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x5566537e2160, 4, 0; + %pushi/vec4 4294967295, 0, 32; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x5566537e2160, 4, 0; + %pushi/vec4 0, 0, 32; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x5566537e2160, 4, 0; + %pushi/vec4 0, 0, 32; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x5566537e2160, 4, 0; + %pushi/vec4 4294967294, 0, 32; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x5566537e2160, 4, 0; + %pushi/vec4 5, 0, 11; + %store/vec4 v0x5566537e7c20_0, 0, 11; +T_0.4 ; + %load/vec4 v0x5566537e7c20_0; + %pad/u 32; + %cmpi/u 1023, 0, 32; + %flag_or 5, 4; + %jmp/0xz T_0.5, 5; + %pushi/vec4 0, 0, 32; + %load/vec4 v0x5566537e7c20_0; + %pad/u 12; + %ix/vec4 4; + %store/vec4a v0x5566537e2160, 4, 0; + %load/vec4 v0x5566537e7c20_0; + %addi 1, 0, 11; + %store/vec4 v0x5566537e7c20_0, 0, 11; + %jmp T_0.4; +T_0.5 ; + %end; + .thread T_0; + .scope S_0x556653785590; +T_1 ; + %wait E_0x55665379d1b0; + %load/vec4 v0x5566537e3630_0; + %inv; + %flag_set/vec4 8; + %jmp/0xz T_1.0, 8; + %load/vec4 v0x5566537e3490_0; + %ix/load 5, 2, 0; + %flag_set/imm 4, 0; + %shiftr 5; + %ix/vec4 4; + %load/vec4a v0x5566537e2f70, 4; + %assign/vec4 v0x5566537e2bf0_0, 0; + %load/vec4 v0x5566537e3490_0; + %addi 4, 0, 32; + %assign/vec4 v0x5566537e3490_0, 0; + %load/vec4 v0x5566537e7820_0; + %inv; + %flag_set/vec4 8; + %jmp/0xz T_1.2, 8; + %load/vec4 v0x5566537e2bf0_0; + %parti/s 5, 21, 6; + %pad/u 7; + %ix/vec4 4; + %load/vec4a v0x5566537e3570, 4; + %assign/vec4 v0x5566537e26b0_0, 0; + %jmp T_1.3; +T_1.2 ; + %load/vec4 v0x5566537e3110_0; + %assign/vec4 v0x5566537e26b0_0, 0; +T_1.3 ; + %load/vec4 v0x5566537e78e0_0; + %inv; + %flag_set/vec4 8; + %jmp/0xz T_1.4, 8; + %load/vec4 v0x5566537e2bf0_0; + %parti/s 5, 16, 6; + %pad/u 7; + %ix/vec4 4; + %load/vec4a v0x5566537e3570, 4; + %assign/vec4 v0x5566537e2790_0, 0; + %jmp T_1.5; +T_1.4 ; + %load/vec4 v0x5566537e3110_0; + %assign/vec4 v0x5566537e2790_0, 0; +T_1.5 ; + %load/vec4 v0x5566537e2bf0_0; + %assign/vec4 v0x5566537e2870_0, 0; + %jmp T_1.1; +T_1.0 ; + %pushi/vec4 32, 0, 32; + %assign/vec4 v0x5566537e2870_0, 0; +T_1.1 ; + %load/vec4 v0x5566537e2950_0; + %pushi/vec4 35, 0, 6; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x5566537e2950_0; + %pushi/vec4 43, 0, 6; + %cmp/e; + %flag_get/vec4 4; + %or; + %flag_set/vec4 8; + %jmp/0xz T_1.6, 8; + %load/vec4 v0x5566537be880_0; + %load/vec4 v0x5566537e2870_0; + %parti/s 1, 15, 5; + %replicate 16; + %load/vec4 v0x5566537e2870_0; + %parti/s 16, 0, 2; + %concat/vec4; draw_concat_vec4 + %add; + %assign/vec4 v0x5566537e2200_0, 0; + %jmp T_1.7; +T_1.6 ; + %load/vec4 v0x5566537e2950_0; + %cmpi/e 0, 0, 6; + %jmp/0xz T_1.8, 4; + %load/vec4 v0x5566537e2870_0; + %parti/s 6, 0, 2; + %dup/vec4; + %pushi/vec4 32, 0, 6; + %cmp/u; + %jmp/1 T_1.10, 6; + %jmp T_1.12; +T_1.10 ; + %load/vec4 v0x5566537be880_0; + %load/vec4 v0x5566537b0640_0; + %add; + %assign/vec4 v0x5566537e2200_0, 0; + %jmp T_1.12; +T_1.12 ; + %pop/vec4 1; +T_1.8 ; +T_1.7 ; + %load/vec4 v0x5566537e2870_0; + %assign/vec4 v0x5566537e2410_0, 0; + %load/vec4 v0x5566537b0640_0; + %assign/vec4 v0x5566537e22e0_0, 0; + %load/vec4 v0x5566537e24f0_0; + %cmpi/e 0, 0, 6; + %jmp/0xz T_1.13, 4; + %load/vec4 v0x5566537e2200_0; + %assign/vec4 v0x5566537e3110_0, 0; + %jmp T_1.14; +T_1.13 ; + %load/vec4 v0x5566537e24f0_0; + %cmpi/e 35, 0, 6; + %jmp/0xz T_1.15, 4; + %load/vec4 v0x5566537e2200_0; + %ix/load 5, 2, 0; + %flag_set/imm 4, 0; + %shiftr 5; + %ix/vec4 4; + %load/vec4a v0x5566537e2160, 4; + %assign/vec4 v0x5566537e3110_0, 0; + %jmp T_1.16; +T_1.15 ; + %load/vec4 v0x5566537e24f0_0; + %cmpi/e 43, 0, 6; + %jmp/0xz T_1.17, 4; + %load/vec4 v0x5566537e22e0_0; + %load/vec4 v0x5566537e2200_0; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %shiftr 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x5566537e2160, 0, 4; +T_1.17 ; +T_1.16 ; +T_1.14 ; + %load/vec4 v0x5566537e2410_0; + %assign/vec4 v0x5566537e3030_0, 0; + %load/vec4 v0x5566537e31f0_0; + %pushi/vec4 0, 0, 6; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x5566537e32d0_0; + %pad/u 32; + %pushi/vec4 0, 0, 32; + %cmp/e; + %flag_get/vec4 4; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_1.19, 8; + %load/vec4 v0x5566537e3110_0; + %load/vec4 v0x5566537e32d0_0; + %pad/u 7; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x5566537e3570, 0, 4; + %jmp T_1.20; +T_1.19 ; + %load/vec4 v0x5566537e31f0_0; + %pushi/vec4 35, 0, 6; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x5566537e33b0_0; + %pad/u 32; + %pushi/vec4 0, 0, 32; + %cmp/e; + %flag_get/vec4 4; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_1.21, 8; + %load/vec4 v0x5566537e3110_0; + %load/vec4 v0x5566537e33b0_0; + %pad/u 7; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x5566537e3570, 0, 4; +T_1.21 ; +T_1.20 ; + %jmp T_1; + .thread T_1; + .scope S_0x5566537b5770; +T_2 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x5566537e7d40_0, 0, 1; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x5566537e7de0_0, 0, 4; + %delay 160, 0; + %vpi_call 2 20 "$finish" {0 0 0}; + %end; + .thread T_2; + .scope S_0x5566537b5770; +T_3 ; + %delay 5, 0; + %load/vec4 v0x5566537e7d40_0; + %inv; + %store/vec4 v0x5566537e7d40_0, 0, 1; + %jmp T_3; + .thread T_3; + .scope S_0x5566537b5770; +T_4 ; + %wait E_0x55665379d1b0; + %load/vec4 v0x5566537e7de0_0; + %addi 1, 0, 4; + %store/vec4 v0x5566537e7de0_0, 0, 4; + %jmp T_4; + .thread T_4; + .scope S_0x5566537b5770; +T_5 ; + %wait E_0x55665379cec0; + %vpi_call 2 36 "$display", "\012\012clock cycle = %d", v0x5566537e7de0_0, " (time = %1.0t)", $time {0 0 0}; + %vpi_call 2 37 "$display", "IF/ID registers\012\011 IF/ID.PC+4 = %h, IF/ID.IR = %h \012", v0x5566537e3490_0, v0x5566537e2bf0_0 {0 0 0}; + %vpi_call 2 38 "$display", "ID/EX registers\012\011 ID/EX.rs = %d, ID/EX.rt = %d", v0x5566537e2a30_0, v0x5566537e2b10_0, "\012\011 ID/EX.A = %h, ID/EX.B = %h", v0x5566537e26b0_0, v0x5566537e2790_0 {0 0 0}; + %vpi_call 2 39 "$display", "\011 ID/EX.op = %h\012", v0x5566537e2950_0 {0 0 0}; + %vpi_call 2 40 "$display", "EX/MEM registers\012\011 EX/MEM.rs = %d, EX/MEM.rt = %d", v0x5566537e2a30_0, v0x5566537e2b10_0, "\012\011 EX/MEM.ALUOut = %h, EX/MEM.ALUout = %h", v0x5566537e2200_0, v0x5566537e22e0_0 {0 0 0}; + %vpi_call 2 41 "$display", "\011 EX/MEM.op = %h\012", v0x5566537e24f0_0 {0 0 0}; + %vpi_call 2 42 "$display", "MEM/WB registers\012\011 MEM/WB.rd = %d, MEM/WB.rt = %d", v0x5566537e32d0_0, v0x5566537e33b0_0, "\012\011 MEM/WB.value = %h", v0x5566537e3110_0 {0 0 0}; + %vpi_call 2 43 "$display", "\011 EX/MEM.op = %h\012", v0x5566537e31f0_0 {0 0 0}; + %jmp T_5; + .thread T_5; + .scope S_0x5566537b5770; +T_6 ; + %vpi_call 2 49 "$dumpfile", "test_mipspipe.vcd" {0 0 0}; + %vpi_call 2 50 "$dumpvars" {0 0 0}; + %end; + .thread T_6; +# The file index is used to find the file name in the following table. +:file_names 4; + "N/A"; + ""; + "test_mipspipe_mp2.v"; + "./mipspipe_mp2.v"; diff --git a/ee4363/mp2/output.txt b/ee4363/mp2/output.txt new file mode 100644 index 0000000..cefb5c6 --- /dev/null +++ b/ee4363/mp2/output.txt @@ -0,0 +1,319 @@ +VCD info: dumpfile test_mipspipe.vcd opened for output. + + +clock cycle = 1 (time = 10) +IF/ID registers + IF/ID.PC+4 = 00000004, IF/ID.IR = 00412820 + +ID/EX registers + ID/EX.rs = 0, ID/EX.rt = 0 + ID/EX.A = xxxxxxxx, ID/EX.B = xxxxxxxx + ID/EX.op = 00 + +EX/MEM registers + EX/MEM.rs = 0, EX/MEM.rt = 0 + EX/MEM.ALUOut = xxxxxxxx, EX/MEM.ALUout = xxxxxxxx + EX/MEM.op = 00 + +MEM/WB registers + MEM/WB.rd = 0, MEM/WB.rt = 0 + MEM/WB.value = xxxxxxxx + EX/MEM.op = 00 + + + +clock cycle = 2 (time = 20) +IF/ID registers + IF/ID.PC+4 = 00000008, IF/ID.IR = 8ca30004 + +ID/EX registers + ID/EX.rs = 2, ID/EX.rt = 1 + ID/EX.A = 00000002, ID/EX.B = 00000001 + ID/EX.op = 00 + +EX/MEM registers + EX/MEM.rs = 2, EX/MEM.rt = 1 + EX/MEM.ALUOut = xxxxxxxx, EX/MEM.ALUout = xxxxxxxx + EX/MEM.op = 00 + +MEM/WB registers + MEM/WB.rd = 0, MEM/WB.rt = 0 + MEM/WB.value = xxxxxxxx + EX/MEM.op = 00 + + + +clock cycle = 3 (time = 30) +IF/ID registers + IF/ID.PC+4 = 0000000c, IF/ID.IR = aca70005 + +ID/EX registers + ID/EX.rs = 5, ID/EX.rt = 3 + ID/EX.A = 00000005, ID/EX.B = 00000003 + ID/EX.op = 23 + +EX/MEM registers + EX/MEM.rs = 5, EX/MEM.rt = 3 + EX/MEM.ALUOut = 00000003, EX/MEM.ALUout = 00000001 + EX/MEM.op = 00 + +MEM/WB registers + MEM/WB.rd = 0, MEM/WB.rt = 0 + MEM/WB.value = xxxxxxxx + EX/MEM.op = 00 + + + +clock cycle = 4 (time = 40) +IF/ID registers + IF/ID.PC+4 = 00000010, IF/ID.IR = 00602020 + +ID/EX registers + ID/EX.rs = 5, ID/EX.rt = 7 + ID/EX.A = 00000005, ID/EX.B = 00000007 + ID/EX.op = 2b + +EX/MEM registers + EX/MEM.rs = 5, EX/MEM.rt = 7 + EX/MEM.ALUOut = 00000007, EX/MEM.ALUout = 00000003 + EX/MEM.op = 23 + +MEM/WB registers + MEM/WB.rd = 5, MEM/WB.rt = 1 + MEM/WB.value = 00000003 + EX/MEM.op = 00 + + + +clock cycle = 5 (time = 50) +IF/ID registers + IF/ID.PC+4 = 00000014, IF/ID.IR = 01093020 + +ID/EX registers + ID/EX.rs = 3, ID/EX.rt = 0 + ID/EX.A = 00000003, ID/EX.B = 00000000 + ID/EX.op = 00 + +EX/MEM registers + EX/MEM.rs = 3, EX/MEM.rt = 0 + EX/MEM.ALUOut = 0000000a, EX/MEM.ALUout = 00000007 + EX/MEM.op = 2b + +MEM/WB registers + MEM/WB.rd = 0, MEM/WB.rt = 3 + MEM/WB.value = ffffffff + EX/MEM.op = 23 + + + +clock cycle = 6 (time = 60) +IF/ID registers + IF/ID.PC+4 = 00000018, IF/ID.IR = ac06000c + +ID/EX registers + ID/EX.rs = 8, ID/EX.rt = 9 + ID/EX.A = 00000008, ID/EX.B = 00000009 + ID/EX.op = 00 + +EX/MEM registers + EX/MEM.rs = 8, EX/MEM.rt = 9 + EX/MEM.ALUOut = ffffffff, EX/MEM.ALUout = 00000000 + EX/MEM.op = 00 + +MEM/WB registers + MEM/WB.rd = 0, MEM/WB.rt = 7 + MEM/WB.value = ffffffff + EX/MEM.op = 2b + + + +clock cycle = 7 (time = 70) +IF/ID registers + IF/ID.PC+4 = 0000001c, IF/ID.IR = 00c05020 + +ID/EX registers + ID/EX.rs = 0, ID/EX.rt = 6 + ID/EX.A = 00000000, ID/EX.B = 00000006 + ID/EX.op = 2b + +EX/MEM registers + EX/MEM.rs = 0, EX/MEM.rt = 6 + EX/MEM.ALUOut = 00000011, EX/MEM.ALUout = 00000009 + EX/MEM.op = 00 + +MEM/WB registers + MEM/WB.rd = 4, MEM/WB.rt = 0 + MEM/WB.value = ffffffff + EX/MEM.op = 00 + + + +clock cycle = 8 (time = 80) +IF/ID registers + IF/ID.PC+4 = 00000020, IF/ID.IR = 8c0b0010 + +ID/EX registers + ID/EX.rs = 6, ID/EX.rt = 0 + ID/EX.A = 00000006, ID/EX.B = 00000000 + ID/EX.op = 00 + +EX/MEM registers + EX/MEM.rs = 6, EX/MEM.rt = 0 + EX/MEM.ALUOut = 0000000c, EX/MEM.ALUout = 00000006 + EX/MEM.op = 2b + +MEM/WB registers + MEM/WB.rd = 6, MEM/WB.rt = 9 + MEM/WB.value = 00000011 + EX/MEM.op = 00 + + + +clock cycle = 9 (time = 90) +IF/ID registers + IF/ID.PC+4 = 00000024, IF/ID.IR = 00000020 + +ID/EX registers + ID/EX.rs = 0, ID/EX.rt = 11 + ID/EX.A = 00000000, ID/EX.B = 0000000b + ID/EX.op = 23 + +EX/MEM registers + EX/MEM.rs = 0, EX/MEM.rt = 11 + EX/MEM.ALUOut = 00000006, EX/MEM.ALUout = 00000000 + EX/MEM.op = 00 + +MEM/WB registers + MEM/WB.rd = 0, MEM/WB.rt = 6 + MEM/WB.value = 00000011 + EX/MEM.op = 2b + + + +clock cycle = 10 (time = 100) +IF/ID registers + IF/ID.PC+4 = 00000028, IF/ID.IR = 002b6020 + +ID/EX registers + ID/EX.rs = 0, ID/EX.rt = 0 + ID/EX.A = 00000000, ID/EX.B = 00000000 + ID/EX.op = 00 + +EX/MEM registers + EX/MEM.rs = 0, EX/MEM.rt = 0 + EX/MEM.ALUOut = 00000010, EX/MEM.ALUout = 0000000b + EX/MEM.op = 23 + +MEM/WB registers + MEM/WB.rd = 10, MEM/WB.rt = 0 + MEM/WB.value = 00000006 + EX/MEM.op = 00 + + + +clock cycle = 11 (time = 110) +IF/ID registers + IF/ID.PC+4 = 0000002c, IF/ID.IR = 00000020 + +ID/EX registers + ID/EX.rs = 1, ID/EX.rt = 11 + ID/EX.A = 00000001, ID/EX.B = 0000000b + ID/EX.op = 00 + +EX/MEM registers + EX/MEM.rs = 1, EX/MEM.rt = 11 + EX/MEM.ALUOut = 00000000, EX/MEM.ALUout = 00000000 + EX/MEM.op = 00 + +MEM/WB registers + MEM/WB.rd = 0, MEM/WB.rt = 11 + MEM/WB.value = fffffffe + EX/MEM.op = 23 + + + +clock cycle = 12 (time = 120) +IF/ID registers + IF/ID.PC+4 = 00000030, IF/ID.IR = 00000020 + +ID/EX registers + ID/EX.rs = 0, ID/EX.rt = 0 + ID/EX.A = 00000000, ID/EX.B = 00000000 + ID/EX.op = 00 + +EX/MEM registers + EX/MEM.rs = 0, EX/MEM.rt = 0 + EX/MEM.ALUOut = 0000000c, EX/MEM.ALUout = 0000000b + EX/MEM.op = 00 + +MEM/WB registers + MEM/WB.rd = 0, MEM/WB.rt = 0 + MEM/WB.value = 00000000 + EX/MEM.op = 00 + + + +clock cycle = 13 (time = 130) +IF/ID registers + IF/ID.PC+4 = 00000034, IF/ID.IR = 00000020 + +ID/EX registers + ID/EX.rs = 0, ID/EX.rt = 0 + ID/EX.A = 00000000, ID/EX.B = 00000000 + ID/EX.op = 00 + +EX/MEM registers + EX/MEM.rs = 0, EX/MEM.rt = 0 + EX/MEM.ALUOut = 00000000, EX/MEM.ALUout = 00000000 + EX/MEM.op = 00 + +MEM/WB registers + MEM/WB.rd = 12, MEM/WB.rt = 11 + MEM/WB.value = 0000000c + EX/MEM.op = 00 + + + +clock cycle = 14 (time = 140) +IF/ID registers + IF/ID.PC+4 = 00000038, IF/ID.IR = 00000020 + +ID/EX registers + ID/EX.rs = 0, ID/EX.rt = 0 + ID/EX.A = 00000000, ID/EX.B = 00000000 + ID/EX.op = 00 + +EX/MEM registers + EX/MEM.rs = 0, EX/MEM.rt = 0 + EX/MEM.ALUOut = 00000000, EX/MEM.ALUout = 00000000 + EX/MEM.op = 00 + +MEM/WB registers + MEM/WB.rd = 0, MEM/WB.rt = 0 + MEM/WB.value = 00000000 + EX/MEM.op = 00 + + + +clock cycle = 15 (time = 150) +IF/ID registers + IF/ID.PC+4 = 0000003c, IF/ID.IR = 00000020 + +ID/EX registers + ID/EX.rs = 0, ID/EX.rt = 0 + ID/EX.A = 00000000, ID/EX.B = 00000000 + ID/EX.op = 00 + +EX/MEM registers + EX/MEM.rs = 0, EX/MEM.rt = 0 + EX/MEM.ALUOut = 00000000, EX/MEM.ALUout = 00000000 + EX/MEM.op = 00 + +MEM/WB registers + MEM/WB.rd = 0, MEM/WB.rt = 0 + MEM/WB.value = 00000000 + EX/MEM.op = 00 + + + +clock cycle = 0 (time = 160) diff --git a/ee4363/mp2/test_mipspipe.vcd b/ee4363/mp2/test_mipspipe.vcd new file mode 100644 index 0000000..3e076d6 --- /dev/null +++ b/ee4363/mp2/test_mipspipe.vcd @@ -0,0 +1,413 @@ +$date + Fri Dec 18 19:19:39 2020 +$end +$version + Icarus Verilog +$end +$timescale + 1s +$end +$scope module test_mipspipe $end +$var reg 1 ! clock $end +$var reg 4 " clock_cycle [3:0] $end +$scope module u_mipspipe_mp2 $end +$var wire 32 # Bin [31:0] $end +$var wire 1 $ STALL $end +$var wire 1 % bypassAfromALUinWB $end +$var wire 1 & bypassAfromLWinWB $end +$var wire 1 ' bypassAfromMEM $end +$var wire 1 ( bypassBfromALUinWB $end +$var wire 1 ) bypassBfromLWinWB $end +$var wire 1 * bypassBfromMEM $end +$var wire 1 + bypassIDEXAfromWB $end +$var wire 1 , bypassIDEXBfromWB $end +$var wire 1 ! clock $end +$var wire 5 - MEMWBrt [4:0] $end +$var wire 5 . MEMWBrd [4:0] $end +$var wire 6 / MEMWBop [5:0] $end +$var wire 5 0 IFIDrt [4:0] $end +$var wire 5 1 IFIDrs [4:0] $end +$var wire 6 2 IFIDop [5:0] $end +$var wire 5 3 IDEXrt [4:0] $end +$var wire 5 4 IDEXrs [4:0] $end +$var wire 6 5 IDEXop [5:0] $end +$var wire 5 6 EXMEMrd [4:0] $end +$var wire 6 7 EXMEMop [5:0] $end +$var wire 32 8 Ain [31:0] $end +$var reg 32 9 EXMEMALUOut [31:0] $end +$var reg 32 : EXMEMB [31:0] $end +$var reg 32 ; EXMEMIR [31:0] $end +$var reg 32 < IDEXA [31:0] $end +$var reg 32 = IDEXB [31:0] $end +$var reg 32 > IDEXIR [31:0] $end +$var reg 32 ? IFIDIR [31:0] $end +$var reg 32 @ MEMWBIR [31:0] $end +$var reg 32 A MEMWBValue [31:0] $end +$var reg 32 B PC [31:0] $end +$var reg 6 C i [5:0] $end +$var reg 11 D j [10:0] $end +$var reg 11 E k [10:0] $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +b10000000000 E +b10000000000 D +b100000 C +b0 B +bx A +b100000 @ +b100000 ? +b100000 > +bx = +bx < +b100000 ; +bx : +bx 9 +bx 8 +b0 7 +b0 6 +b0 5 +b0 4 +b0 3 +b0 2 +b0 1 +b0 0 +b0 / +b0 . +b0 - +1, +1+ +0* +0) +0( +0' +0& +0% +0$ +bx # +b0 " +0! +$end +#5 +0+ +0, +b10 1 +b1 0 +b100 B +b10000010010100000100000 ? +b1 " +1! +#10 +0! +#15 +b10 8 +b10 4 +b1 3 +b1 # +b101 1 +b11 0 +b100011 2 +b10000010010100000100000 > +b1 = +b10 < +b1000 B +b10001100101000110000000000000100 ? +b10 " +1! +#20 +0! +#25 +1' +b11 8 +b101 6 +b101 4 +b11 3 +b100011 5 +b11 # +b111 0 +b101011 2 +b1 : +b10000010010100000100000 ; +b11 9 +b10001100101000110000000000000100 > +b11 = +b101 < +b1100 B +b10101100101001110000000000000101 ? +b11 " +1! +#30 +0! +#35 +0' +b101 . +b1 - +b0 6 +b100011 7 +b101 8 +b111 3 +b101011 5 +b111 # +b11 1 +b0 0 +b0 2 +b10000010010100000100000 @ +b11 A +b11 : +b10001100101000110000000000000100 ; +b111 9 +b10101100101001110000000000000101 > +b111 = +b10000 B +b11000000010000000100000 ? +b100 " +1! +#40 +0! +#45 +1& +b11111111111111111111111111111111 8 +b0 . +b11 - +b100011 / +b101011 7 +b11 4 +b0 3 +b0 5 +b0 # +b1000 1 +b1001 0 +b10001100101000110000000000000100 @ +b11111111111111111111111111111111 A +b111 : +b10101100101001110000000000000101 ; +b1010 9 +b11000000010000000100000 > +b0 = +b11 < +b10100 B +b1000010010011000000100000 ? +b101 " +1! +#50 +0! +#55 +b1000 8 +0& +b111 - +b101011 / +b100 6 +b0 7 +b1000 4 +b1001 3 +b1001 # +b0 1 +b110 0 +b101011 2 +b10101100101001110000000000000101 @ +b0 : +b11000000010000000100000 ; +b11111111111111111111111111111111 9 +b1000010010011000000100000 > +b1001 = +b1000 < +b11000 B +b10101100000001100000000000001100 ? +b110 " +1! +#60 +0! +#65 +b0 8 +b100 . +b0 - +b0 / +b110 6 +b0 4 +b110 3 +b101011 5 +b110 # +b110 1 +b0 0 +b0 2 +b11000000010000000100000 @ +b1001 : +b1000010010011000000100000 ; +b10001 9 +b10101100000001100000000000001100 > +b110 = +b0 < +b11100 B +b110000000101000000100000 ? +b111 " +1! +#70 +0! +#75 +b110 8 +b110 . +b1001 - +b0 6 +b101011 7 +b110 4 +b0 3 +b0 5 +b0 # +b0 1 +b1011 0 +b100011 2 +b1000010010011000000100000 @ +b10001 A +b110 : +b10101100000001100000000000001100 ; +b1100 9 +b110000000101000000100000 > +b0 = +b110 < +b100000 B +b10001100000010110000000000010000 ? +b1000 " +1! +#80 +0! +#85 +0$ +b0 8 +b0 . +b110 - +b101011 / +b1010 6 +b0 7 +b0 4 +b1011 3 +b100011 5 +b1011 # +b0 0 +b0 2 +b10101100000001100000000000001100 @ +b0 : +b110000000101000000100000 ; +b110 9 +b10001100000010110000000000010000 > +b1011 = +b0 < +b100100 B +b100000 ? +b1001 " +1! +#90 +0! +#95 +b1010 . +b0 - +b0 / +b0 6 +b100011 7 +b0 3 +b0 5 +b0 # +b1 1 +b1011 0 +b110000000101000000100000 @ +b110 A +b1011 : +b10001100000010110000000000010000 ; +b10000 9 +b100000 > +b0 = +b101000 B +b1010110110000000100000 ? +b1010 " +1! +#100 +0! +#105 +b1 8 +b0 . +b1011 - +b100011 / +b0 7 +b1 4 +b1011 3 +b1011 # +b0 1 +b0 0 +b10001100000010110000000000010000 @ +b11111111111111111111111111111110 A +b0 : +b100000 ; +b0 9 +b1010110110000000100000 > +b1011 = +b1 < +b101100 B +b100000 ? +b1011 " +1! +#110 +0! +#115 +1+ +1, +b0 8 +b0 - +b0 / +b1100 6 +b0 4 +b0 3 +b0 # +b100000 @ +b0 A +b1011 : +b1010110110000000100000 ; +b1100 9 +b100000 > +b0 = +b0 < +b110000 B +b1100 " +1! +#120 +0! +#125 +0+ +0, +b1100 . +b1011 - +b0 6 +b1010110110000000100000 @ +b1100 A +b0 : +b100000 ; +b0 9 +b110100 B +b1101 " +1! +#130 +0! +#135 +1+ +1, +b0 . +b0 - +b100000 @ +b0 A +b111000 B +b1110 " +1! +#140 +0! +#145 +b111100 B +b1111 " +1! +#150 +0! +#155 +b1000000 B +b0 " +1! +#160 +0! diff --git a/ee4363/mp2/test_mipspipe_mp2.v b/ee4363/mp2/test_mipspipe_mp2.v new file mode 100644 index 0000000..f184011 --- /dev/null +++ b/ee4363/mp2/test_mipspipe_mp2.v @@ -0,0 +1,53 @@ +// +// Test bench for the mipspipe +// Boram Lee +// + +`include "mipspipe_mp2.v" + +module test_mipspipe; + + reg clock; + reg [3:0] clock_cycle; + +// instantiate pipeline module + mipspipe_mp2 u_mipspipe_mp2(clock); + +// initialize clock and cycle counter + initial begin + clock = 0; + clock_cycle=4'h0; + #160 $finish; + end + +// 10 unit clock cycle + always + #5 clock = ~clock; + + always @(posedge clock) + begin + clock_cycle=clock_cycle+1; + end + + +// display contents of pipeline latches at the end of each clock cycle + always @(negedge clock) + begin + $display("\n\nclock cycle = %d",clock_cycle," (time = %1.0t)",$time); + $display("IF/ID registers\n\t IF/ID.PC+4 = %h, IF/ID.IR = %h \n", u_mipspipe_mp2.PC, u_mipspipe_mp2.IFIDIR); + $display("ID/EX registers\n\t ID/EX.rs = %d, ID/EX.rt = %d",u_mipspipe_mp2.IDEXrs,u_mipspipe_mp2.IDEXrt,"\n\t ID/EX.A = %h, ID/EX.B = %h",u_mipspipe_mp2.IDEXA,u_mipspipe_mp2.IDEXB); + $display("\t ID/EX.op = %h\n",u_mipspipe_mp2.IDEXop); + $display("EX/MEM registers\n\t EX/MEM.rs = %d, EX/MEM.rt = %d",u_mipspipe_mp2.IDEXrs,u_mipspipe_mp2.IDEXrt,"\n\t EX/MEM.ALUOut = %h, EX/MEM.ALUout = %h",u_mipspipe_mp2.EXMEMALUOut,u_mipspipe_mp2.EXMEMB); + $display("\t EX/MEM.op = %h\n",u_mipspipe_mp2.EXMEMop); + $display("MEM/WB registers\n\t MEM/WB.rd = %d, MEM/WB.rt = %d",u_mipspipe_mp2.MEMWBrd,u_mipspipe_mp2.MEMWBrt,"\n\t MEM/WB.value = %h",u_mipspipe_mp2.MEMWBValue); + $display("\t EX/MEM.op = %h\n",u_mipspipe_mp2.MEMWBop); + end + +// log to a vcd (variable change dump) file + initial + begin + $dumpfile("test_mipspipe.vcd"); + $dumpvars; + end + +endmodule -- cgit v1.2.3