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authorRossTheRoss <mstrapp@protonmail.com>2020-12-18 19:42:33 -0600
committerRossTheRoss <mstrapp@protonmail.com>2020-12-18 19:42:33 -0600
commit03e522d164dfd9e49a1fbc2f23134cdcb1544286 (patch)
tree4b20ba96084ca10a78a0b1c97cb365e268724f90
parentadd things (diff)
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-rw-r--r--ee4363/mp1.zipbin90454 -> 0 bytes
-rw-r--r--ee4363/mp2/mipspipe_mp2.v2
2 files changed, 1 insertions, 1 deletions
diff --git a/ee4363/mp1.zip b/ee4363/mp1.zip
deleted file mode 100644
index 8625c42..0000000
--- a/ee4363/mp1.zip
+++ /dev/null
Binary files differ
diff --git a/ee4363/mp2/mipspipe_mp2.v b/ee4363/mp2/mipspipe_mp2.v
index 784b669..9ea9fc2 100644
--- a/ee4363/mp2/mipspipe_mp2.v
+++ b/ee4363/mp2/mipspipe_mp2.v
@@ -43,7 +43,7 @@ module mipspipe_mp2 (clock);
assign bypassAfromLWinWB = (IDEXrs == MEMWBIR[20:16]) & (IDEXrs!=0) & (MEMWBop==LW);
// The bypass to input B from the WB stage for an LW operation
assign bypassBfromLWinWB = 0;
- //Stall in case of WB
+ //Stall to bypass A or B if need b (I'm not sorry)
assign bypassIDEXAfromWB = ((MEMWBIR != nop) & (IFIDIR != nop) & (IFIDrs == MEMWBrt) & (MEMWBop == LW)) |
((MEMWBop == ALUop) & (MEMWBrd == IFIDrs));
assign bypassIDEXBfromWB = ((MEMWBIR != nop) & (IFIDIR != nop) & (IFIDrt == MEMWBrt) & (MEMWBop == LW)) |