diff options
| author | RossTheRoss <mstrapp@protonmail.com> | 2021-01-17 12:57:21 -0600 |
|---|---|---|
| committer | RossTheRoss <mstrapp@protonmail.com> | 2021-01-17 12:57:21 -0600 |
| commit | dde37c31a72f4773e95faf8223ef450440bdb62c (patch) | |
| tree | e238837d1d2f364b95483f6281960f9483078c1a /OLD | |
| parent | IDK (diff) | |
| download | homework-dde37c31a72f4773e95faf8223ef450440bdb62c.tar homework-dde37c31a72f4773e95faf8223ef450440bdb62c.tar.gz homework-dde37c31a72f4773e95faf8223ef450440bdb62c.tar.bz2 homework-dde37c31a72f4773e95faf8223ef450440bdb62c.tar.lz homework-dde37c31a72f4773e95faf8223ef450440bdb62c.tar.xz homework-dde37c31a72f4773e95faf8223ef450440bdb62c.tar.zst homework-dde37c31a72f4773e95faf8223ef450440bdb62c.zip | |
get rid of that trash
Diffstat (limited to 'OLD')
40 files changed, 3858 insertions, 0 deletions
diff --git a/OLD/csci4061/091420_breakout/Makefile b/OLD/csci4061/091420_breakout/Makefile new file mode 100644 index 0000000..1e807a9 --- /dev/null +++ b/OLD/csci4061/091420_breakout/Makefile @@ -0,0 +1,16 @@ +CC=gcc +CFLAGS=-I./include +OBJ=main.o name.o address.o major.o +EXE=w2.out + +all: $(EXE) + +$(EXE): $(OBJ) + $(CC) -o $@ $^ $(CFLAGS) + +%.o: %.c + $(CC) -c -o $@ $< $(CFLAGS) +clean: + rm *.o $(EXE) +run: + ./$(EXE)
\ No newline at end of file diff --git a/OLD/csci4061/091420_breakout/address.c b/OLD/csci4061/091420_breakout/address.c new file mode 100644 index 0000000..3f36f70 --- /dev/null +++ b/OLD/csci4061/091420_breakout/address.c @@ -0,0 +1,15 @@ +#include "include/main.h" +#include "include/address.h" + +/* + * Write getAddress function + * void getAddress(char * address); + * Prints a prompt "Enter your address: " to get an address, + * Reads in the user's address + */ + +void getAddress(char * address) { + printf("Enter your address: "); + fgets(address, maxLen, stdin); + fflush(stdin); +}
\ No newline at end of file diff --git a/OLD/csci4061/091420_breakout/include/address.h b/OLD/csci4061/091420_breakout/include/address.h new file mode 100644 index 0000000..97a4c03 --- /dev/null +++ b/OLD/csci4061/091420_breakout/include/address.h @@ -0,0 +1,6 @@ +#ifndef INC_091420_BREAKOUT_ADDRESS_H +#define INC_091420_BREAKOUT_ADDRESS_H + +void getAddress(char * address); + +#endif //INC_091420_BREAKOUT_ADDRESS_H diff --git a/OLD/csci4061/091420_breakout/include/main.h b/OLD/csci4061/091420_breakout/include/main.h new file mode 100644 index 0000000..6f7f6fe --- /dev/null +++ b/OLD/csci4061/091420_breakout/include/main.h @@ -0,0 +1,7 @@ +#ifndef INC_091420_BREAKOUT_MAIN_H +#define INC_091420_BREAKOUT_MAIN_H + +#include <stdio.h> +static const int maxLen = 100; + +#endif //INC_091420_BREAKOUT_MAIN_H diff --git a/OLD/csci4061/091420_breakout/include/major.h b/OLD/csci4061/091420_breakout/include/major.h new file mode 100644 index 0000000..e649ea6 --- /dev/null +++ b/OLD/csci4061/091420_breakout/include/major.h @@ -0,0 +1,6 @@ +#ifndef INC_091420_BREAKOUT_MAJOR_H +#define INC_091420_BREAKOUT_MAJOR_H + +void getMajor(char * major); + +#endif //INC_091420_BREAKOUT_MAJOR_H diff --git a/OLD/csci4061/091420_breakout/include/name.h b/OLD/csci4061/091420_breakout/include/name.h new file mode 100644 index 0000000..2bb96aa --- /dev/null +++ b/OLD/csci4061/091420_breakout/include/name.h @@ -0,0 +1,6 @@ +#ifndef INC_091420_BREAKOUT_NAME_H +#define INC_091420_BREAKOUT_NAME_H + +void getName(char * name); + +#endif //INC_091420_BREAKOUT_NAME_H diff --git a/OLD/csci4061/091420_breakout/main.c b/OLD/csci4061/091420_breakout/main.c new file mode 100644 index 0000000..aeb989e --- /dev/null +++ b/OLD/csci4061/091420_breakout/main.c @@ -0,0 +1,36 @@ +/* + * Recitation section number: + * Breakout Group Number: + * Member name (email address): + * Member name (email address): + * Member name (email address): + * Member name (email address): + * Member name (email address): + * Member name (email address): + * Member name (email address): + */ + +#include "include/main.h" +#include "include/name.h" +#include "include/address.h" +#include "include/major.h" + +int main() { + + char name[maxLen]; + char address[maxLen]; + char major[maxLen]; + + printf("Hi there! \nTell me more about you.\n"); + getName(name); + getAddress(address); + getMajor(major); + + printf("Thanks for your information!\n"); + printf("Your name: %s", name); + printf("Your address: %s", address); + printf("Your major: %s", major); + printf("Bye!\n"); + + return 0; +}
\ No newline at end of file diff --git a/OLD/csci4061/091420_breakout/major.c b/OLD/csci4061/091420_breakout/major.c new file mode 100644 index 0000000..cfc9cef --- /dev/null +++ b/OLD/csci4061/091420_breakout/major.c @@ -0,0 +1,15 @@ +#include "include/main.h" +#include "include/major.h" + +/* + * Write getMajor function + * void getMajor(char * major); + * Prints a prompt "Enter your major: " to get an major, + * Reads in the user's major + */ + +void getMajor(char * major) { + printf("Enter your major: "); + fgets(major, maxLen, stdin); + fflush(stdin); +}
\ No newline at end of file diff --git a/OLD/csci4061/091420_breakout/name.c b/OLD/csci4061/091420_breakout/name.c new file mode 100644 index 0000000..97c2a9d --- /dev/null +++ b/OLD/csci4061/091420_breakout/name.c @@ -0,0 +1,8 @@ +#include "include/main.h" +#include "include/name.h" + +void getName(char * name) { + printf("Enter your name: "); + fgets(name, maxLen, stdin); + fflush(stdin); +}
\ No newline at end of file diff --git a/OLD/csci4061/092120_breakout/main.c b/OLD/csci4061/092120_breakout/main.c new file mode 100644 index 0000000..8d8e08d --- /dev/null +++ b/OLD/csci4061/092120_breakout/main.c @@ -0,0 +1,50 @@ +/* +CSci 4061 - Recitation 2 - 21st Sept 2020 +Breakout 1 +An iditoic loner's lone attempt +*/ + +#include <stdio.h> +#include <stdlib.h> +#include <sys/types.h> +#include <sys/wait.h> +#include <unistd.h> +#include <errno.h> + +int main(int argc, char **argv) { + // take 'n' from the input and convert to integer + // hint: see cmd slide + if (argc < 2) { + printf("USAGE: ./main int\n"); + return -1; + } + int n = strtol(argv[1], NULL, 10); + // for i in n + // create child process + // print pid //hint: check week 2 slides + // call execl to print 'hello there' using 'echo' //hint: check recitation slide + pid_t pid; + for (int i=0; i<n; i++) { + pid = fork(); + if (pid == 0) { + + } else { +printf("%d\n", getpid()); + execl("/bin/echo", "/bin/echo", "hello", "there", NULL); + } + } + // parent waits for all child processes to terminate + for (int i=0; i<n; i++) { + wait(NULL); + } + // parent create child process + // call execv on 'ptime' executable // hint: similar to 'echo' usage in slide + pid = fork(); + if (pid != 0) { + char *args[] = {"./ptime", NULL}; + execv(*args, args); + } + // parent waits for child to complete + waitpid(pid, NULL, 0); + return 0; +}
\ No newline at end of file diff --git a/OLD/csci4061/092820_breakout/main.c b/OLD/csci4061/092820_breakout/main.c new file mode 100644 index 0000000..0757a06 --- /dev/null +++ b/OLD/csci4061/092820_breakout/main.c @@ -0,0 +1,36 @@ +/* +* Recitation Section Number: +* Breakout Number: +* Member Name +* Member Name +* Member Name +* Member Name +*/ + + +#include<stdio.h> +#include <stdlib.h> // For exit() + + +int main() { + + //STEP 1 + //Your code to open the file copy the file and close the file + FILE* fread = fopen("sample.txt", "r"); + FILE* fwrite = fopen("sample_copy.txt", "w"); + int bufsize = 30; + char str[bufsize]; + fgets(str, bufsize, fread); + fputs(str, fwrite); + + //STEP 2 + //Your code to read the text and add the numbers + char* text = "sample text 2 4 5"; + int a=0, b=0, c=0; + char* waste1; char* waste2; + sscanf(text, "%s %s %d %d %d", &waste1, &waste2, &a, &b, &c); + printf("%d\n", a+b+c); + + return 0; + +}
\ No newline at end of file diff --git a/OLD/csci4061/092820_breakout/sample.txt b/OLD/csci4061/092820_breakout/sample.txt new file mode 100644 index 0000000..e568c7b --- /dev/null +++ b/OLD/csci4061/092820_breakout/sample.txt @@ -0,0 +1 @@ +abcdefghijklmnopqrstuvwxya
\ No newline at end of file diff --git a/OLD/csci4061/092820_breakout/sample_copy.txt b/OLD/csci4061/092820_breakout/sample_copy.txt new file mode 100644 index 0000000..e568c7b --- /dev/null +++ b/OLD/csci4061/092820_breakout/sample_copy.txt @@ -0,0 +1 @@ +abcdefghijklmnopqrstuvwxya
\ No newline at end of file diff --git a/OLD/csci4061/100520_breakout/exercise.c b/OLD/csci4061/100520_breakout/exercise.c new file mode 100644 index 0000000..6d560d5 --- /dev/null +++ b/OLD/csci4061/100520_breakout/exercise.c @@ -0,0 +1,47 @@ +/* +* Recitation Section Number: +* Breakout Number: +* Member Name +* Member Name +* Member Name +* Member Name +*/ + +#include <stdio.h> +#include <stdlib.h> +#include <unistd.h> +#include <errno.h> +#include <sys/stat.h> +#include <fcntl.h> +#include <string.h> +#define BUFSIZE 20 +#define PERM 0644 +int main(int argc, char *argv[]) { + int infile; char buffer[BUFSIZE]; + // create/open a file named write.txt + infile = open("write.txt", O_CREAT | O_RDWR | O_TRUNC, PERM); + // write hello world to write.txtS + write(infile, "hello world\n", 12); + // spawn a child process and use this child process to reroute stdout to write.txt + pid_t pid = fork(); + if (!pid) { + dup2(infile, 1); + } + // print pid + printf("Process %d\n", pid); + + // use the child process spawned previously to read the contents from write.txt, restore output to stdout + // and then prints the contents of write.txt to stdout. + if (!pid) { + read(infile, buffer, 20); + int stdout = open("/dev/tty", O_WRONLY); + dup2(1, stdout); + printf("%s\n", buffer); + return 0; + } + // print pid + printf("%d\n", pid); + // close the file write.txt + close(infile); + return 0; +}
\ No newline at end of file diff --git a/OLD/csci4061/101220_breakout/exercise.c b/OLD/csci4061/101220_breakout/exercise.c new file mode 100644 index 0000000..b6e863e --- /dev/null +++ b/OLD/csci4061/101220_breakout/exercise.c @@ -0,0 +1,82 @@ +#include <stdio.h> +#include <stdlib.h> +#include <sys/types.h> +#include <sys/wait.h> +#include <sys/stat.h> +#include <unistd.h> +#include <fcntl.h> +#include <dirent.h> +#include <string.h> +#include <time.h> + +int numOfEntry(char *path) +{ + int count = 0; + DIR *dir = opendir(path); + struct dirent *entry; + + while ((entry = readdir(dir)) != NULL) + { + + if (!strcmp(entry->d_name, ".") || !strcmp(entry->d_name, "..")) + continue; + + count++; + } + + closedir(dir); + + return count; +} + +int main(int argc, char **argv) +{ + + if (argc < 2) + { + printf("Pass the path as an argument to the program"); + exit(1); + } + + char *path = argv[1]; + + DIR *dir = opendir(path); + if (dir == NULL) + { + printf("The path passed is invalid"); + return -1; + } + struct dirent *entry; + + while ((entry = readdir(dir)) != NULL) + { + + if (!strcmp(entry->d_name, ".") || !strcmp(entry->d_name, "..")) + continue; + + if (entry->d_type == DT_DIR) + { + char next[strlen(path) + strlen(entry->d_name) + 2]; + next[0] = '\0'; + strcat(next, path); + strcat(next, "/"); + strcat(next, entry->d_name); + printf("Directory: %s\n\tEntries: %d\n", entry->d_name, numOfEntry(next)); + } + else if (entry->d_type == DT_REG) + { + struct stat *buf = (struct stat *)malloc(sizeof(struct stat)); + stat(entry->d_name, buf); + printf("Regular File: %s\n\tOwner: %d\n\tSize: %f\n\tInode: %llu\n", + entry->d_name, buf->st_uid, (double)buf->st_size, buf->st_ino); + free(buf); + } + else + { + printf("File: %s\n\tType:%hhu\n", entry->d_name, entry->d_type); + } + } + + closedir(dir); + return 0; +}
\ No newline at end of file diff --git a/OLD/csci4061/101920_breakout/pipe_template.c b/OLD/csci4061/101920_breakout/pipe_template.c new file mode 100644 index 0000000..2c37941 --- /dev/null +++ b/OLD/csci4061/101920_breakout/pipe_template.c @@ -0,0 +1,65 @@ +// ----------------------------------------------------------------------------- +// Pipes +// +// Write a program that creates a child process and pipes the string +// "hello child" to the child to be printed. The parent should wait for the +// child to terminate +// +// Template: Implement the TODOs +// +// Expected output: +// Parent Sending: hello child +// Child Received: hello child +// ----------------------------------------------------------------------------- + +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <sys/wait.h> +#include <unistd.h> + +int main(void) { + // Open pipe + int ends[2]; + pipe(ends); + + char string_to_send[] = "hello child"; + int bytes_to_send_recv = strlen(string_to_send) + 1; + + // Create child process + pid_t pid = fork(); + if (pid < 0) { + // Error + fprintf(stderr, "ERROR: Failed to fork\n"); + } + else if (pid > 0) { + // Parent + printf("Parent Sending: %s\n", string_to_send); + + // Parent doesn't need read file descriptor + close(ends[0]); + // Write the string to the pipe + write(ends[1], string_to_send, bytes_to_send_recv); + // Done writing + close(ends[1]); + // Wait for child to terminate + wait(NULL); + } + else { + // Child + + char *recv_buffer = malloc(bytes_to_send_recv); + + // Child doesn't need write file descriptor + close(ends[1]); + // Read the string from the pipe + read(ends[0], recv_buffer, bytes_to_send_recv); + // Done reading + close(ends[0]); + // Print result + printf("Child Received: %s\n", recv_buffer); + free(recv_buffer); + } + + return 0; +} diff --git a/OLD/csci4061/102620_breakout/msg_queue_template.c b/OLD/csci4061/102620_breakout/msg_queue_template.c new file mode 100644 index 0000000..af026f3 --- /dev/null +++ b/OLD/csci4061/102620_breakout/msg_queue_template.c @@ -0,0 +1,108 @@ +/* +* Recitation Section Number: 02 +* Breakout Number: 05 +* Graden Hill (hill1582) +* Gustav Baumgart (baumg260) +* Matt Strapp (strap012) +* Skylan Recnana (recan001) +*/ + +#include <stdio.h> +#include <sys/ipc.h> +#include <sys/msg.h> +#include <sys/wait.h> +#include <zconf.h> +#include <string.h> +#include <stdlib.h> + +#define PERM 0666 +#define MSGSIZE 100 +#define NCHILD 3 + +// structure for message queue +typedef struct msg_buffer { + long mtype; + char mtext[MSGSIZE]; +} message; + +int main(void) { + key_t key; + int msgid; + pid_t pid1, pid2; + message msg; + + // generate unique key + key = ftok("recitation", 4061); + + // creates a message queue + msgid = msgget(key, PERM | IPC_CREAT); + + + // sender child process + pid1 = fork(); + if (pid1 == 0) { + for (int i = 0; i < NCHILD; i++) { + msg.mtype = 111; + memset(msg.mtext, '\0', MSGSIZE); + sprintf(msg.mtext, "Hello child %d", i); + // send message to other child processes + msgsnd(msgid, &msg, MSGSIZE, 0); + + + // display the message + printf("[%d] Data sent is : %s \n", i, msg.mtext); + } + + for (int i = 0; i < NCHILD; i++) { + msg.mtype = 222; + memset(msg.mtext, '\0', MSGSIZE); + sprintf(msg.mtext, "Message %d", i); + // send message to other child processes + msgsnd(msgid, &msg, MSGSIZE, 0); + + // display the message + printf("[%d] Data sent is : %s \n", i, msg.mtext); + } + + for (int i = 0; i < NCHILD; i++) { + msg.mtype = 333; + memset(msg.mtext, '\0', MSGSIZE); + sprintf(msg.mtext, "Bye %d", i); + // send message to other child processes + msgsnd(msgid, &msg, MSGSIZE, 0); + + // display the message + printf("[%d] Data sent is : %s \n", i, msg.mtext); + } + + exit(0); + } else if (pid1 < 0) { + printf("fork1 error\n"); + return -1; + } + + // receiver child processes + for (int j = 0; j < NCHILD; j++) { + if ((pid2 = fork()) == 0) { + // receive message + msgrcv(msgid, &msg, MSGSIZE, 222, 0); + + + // display the message + printf("[%d] Data received is : %s \n", j, msg.mtext); + + exit(0); + } else if (pid2 < 0) { + printf("fork2 error\n"); + return -1; + } + } + + while (wait(NULL) > 0); + + // to destroy the message queue + msgctl(msgid, IPC_RMID, NULL); + + + return 0; +}
\ No newline at end of file diff --git a/OLD/csci4061/110920_breakout/chap8/Makefile b/OLD/csci4061/110920_breakout/chap8/Makefile new file mode 100644 index 0000000..bd92bec --- /dev/null +++ b/OLD/csci4061/110920_breakout/chap8/Makefile @@ -0,0 +1,12 @@ +pgm81: pgm_8_1.c + gcc pgm_8_1.c -lm -o out + ./out 5 + +pgm85: pgm_8_5.c + gcc pgm_8_5.c -lm -o out + ./out + +.PHONY: clean + +clean: + rm out diff --git a/OLD/csci4061/110920_breakout/chap8/pgm_8_1.c b/OLD/csci4061/110920_breakout/chap8/pgm_8_1.c new file mode 100644 index 0000000..a979bb6 --- /dev/null +++ b/OLD/csci4061/110920_breakout/chap8/pgm_8_1.c @@ -0,0 +1,42 @@ +// Program 8.1 + +#include <math.h> +#include <signal.h> +#include <stdio.h> +#include <stdlib.h> +#include <unistd.h> + +int main(int argc, char *argv[]) { + int i; + sigset_t intmask; + int repeatfactor; + double y = 0.0; + + if (argc != 2) { + fprintf(stderr, "Usage: %s repeatfactor\n", argv[0]); + return 1; + } + repeatfactor = atoi(argv[1]); + if ((sigemptyset(&intmask) == -1) || (sigaddset(&intmask, SIGINT) == -1)){ + perror("Failed to initialize the signal mask"); + return 1; + } + for ( ; ; ) { + if (sigprocmask(SIG_BLOCK, &intmask, NULL) == -1) + break; + fprintf(stderr, "SIGINT signal blocked\n"); + for (i = 0; i < repeatfactor; i++) + y += sin((double)i); + fprintf(stderr, "Blocked calculation is finished, y = %f\n", y); + sleep(3); + if (sigprocmask(SIG_UNBLOCK, &intmask, NULL) == -1) + break; + fprintf(stderr, "SIGINT signal unblocked\n"); + for (i = 0; i < repeatfactor; i++) + y += sin((double)i); + fprintf(stderr, "Unblocked calculation is finished, y=%f\n", y); + sleep(3); + } + perror("Failed to change signal mask"); + return 1; +}
\ No newline at end of file diff --git a/OLD/csci4061/110920_breakout/chap8/pgm_8_5.c b/OLD/csci4061/110920_breakout/chap8/pgm_8_5.c new file mode 100644 index 0000000..b20cdfa --- /dev/null +++ b/OLD/csci4061/110920_breakout/chap8/pgm_8_5.c @@ -0,0 +1,43 @@ +// Program 8.5 + +#include <math.h> +#include <signal.h> +#include <stdio.h> +#include <stdlib.h> + +static volatile sig_atomic_t doneflag = 0; + +/* ARGSUSED */ +static void setdoneflag(int signo) { + doneflag = 1; +} + +int main (void) { + struct sigaction act; + int count = 0; + double sum = 0; + double x; + + act.sa_handler = setdoneflag; /* set up signal handler */ + act.sa_flags = 0; + if ((sigemptyset(&act.sa_mask) == -1) || + (sigaction(SIGINT, &act, NULL) == -1)) { + perror("Failed to set SIGINT handler"); + return 1; + } + + while (!doneflag) { + x = (rand() + 0.5)/(RAND_MAX + 1.0); + sum += sin(x); + count++; + printf("Count is %d and average is %f\n", count, sum/count); + sleep(3); + } + + printf("Program terminating ...\n"); + if (count == 0) + printf("No values calculated yet\n"); + else + printf("Count is %d and average is %f\n", count, sum/count); + return 0; +}
\ No newline at end of file diff --git a/OLD/csci4061/110920_breakout/sol1.c b/OLD/csci4061/110920_breakout/sol1.c new file mode 100644 index 0000000..d33b0df --- /dev/null +++ b/OLD/csci4061/110920_breakout/sol1.c @@ -0,0 +1,37 @@ +/* +* Recitation Section Number: 9 +* Breakout Number: 6 +* Audrey Hebert (heber169) +* Qiyu Tian (tian0068) +* Mouhari Mouhamed (mouha003) +* Matt Strapp (strap012) +*/ + +#include <stdio.h> +#include <signal.h> +#include <unistd.h> +#include <time.h> + +void infinitePrint() { + + static int count = 0; + printf("%ld: Count = %d\n", time(NULL), ++count); + sleep(1); +} + +int main() { + + // ------------------sol1.c----------------- + // initialize new sigset - sigset_t, sigemptyset + sigset_t sigset; + sigemptyset(&sigset); + // add SIGINT to sigset - sigaddset + sigaddset(&sigset, SIGINT); + // block SIGINT - sigprocmask + sigprocmask(SIG_BLOCK, &sigset, NULL); + // Do not modify the while loop and infinitePrint() + // ----------------------------------------- + + /* Print infinitely. */ + while (1) infinitePrint(); +}
\ No newline at end of file diff --git a/OLD/csci4061/110920_breakout/sol2.c b/OLD/csci4061/110920_breakout/sol2.c new file mode 100644 index 0000000..04dad3e --- /dev/null +++ b/OLD/csci4061/110920_breakout/sol2.c @@ -0,0 +1,52 @@ +/* +* Recitation Section Number: 9 +* Breakout Number: 6 +* Audrey Hebert (heber169) +* Qiyu Tian (tian0068) +* Mouhari Mouhamed (mouha003) +* Matt Strapp (strap012) +*/ + +#include <stdio.h> +#include <signal.h> +#include <unistd.h> +#include <time.h> + +// Remember the usage of sig_atomic_t in the recitation example +static volatile sig_atomic_t doneflag = 0; + +static void setdoneflag(int signo) { + doneflag = doneflag ^ 1; +} + +void infinitePrint() { + + static int count = 0; + printf("%ld: Count = %d\n", time(NULL), ++count); + sleep(1); +} + +int main() { + + // ------------------sol2.c----------------- + // setup signal handler - sigaction struct, sigemptyset, + struct sigaction act; + sigset_t sigset; + // specify action associated with SIGNT - sigaction() + act.sa_handler = setdoneflag; /* set up signal handler */ + act.sa_flags = 0; + if ((sigemptyset(&act.sa_mask) == -1) || + (sigaction(SIGINT, &act, NULL) == -1)) + { + perror("Failed to set SIGINT handler"); + return 1; + } + // You are free to modify the while loop but not the infinitePrint() + // ----------------------------------------- + + /* Print infinitely. */ + while (1) { + if (!doneflag) + infinitePrint(); + } +}
\ No newline at end of file diff --git a/OLD/csci4061/110920_breakout/zip/sol1.c b/OLD/csci4061/110920_breakout/zip/sol1.c new file mode 100644 index 0000000..ca60c50 --- /dev/null +++ b/OLD/csci4061/110920_breakout/zip/sol1.c @@ -0,0 +1,37 @@ +/* +* Recitation Section Number: 9 +* Breakout Number: +* Audrey Hebert (heber169) +* Qiyu Tian (tian0068) +* Mouhari Mouhamed (mouha003) +* Matt Strapp (strap012) +*/ + +#include <stdio.h> +#include <signal.h> +#include <unistd.h> +#include <time.h> + +void infinitePrint() { + + static int count = 0; + printf("%ld: Count = %d\n", time(NULL), ++count); + sleep(1); +} + +int main() { + + // ------------------sol1.c----------------- + // initialize new sigset - sigset_t, sigemptyset + sigset_t sigset; + sigemptyset(&sigset); + // add SIGINT to sigset - sigaddset + sigaddset(&sigset, SIGINT); + // block SIGINT - sigprocmask + sigprocmask(SIG_BLOCK, &sigset, NULL); + // Do not modify the while loop and infinitePrint() + // ----------------------------------------- + + /* Print infinitely. */ + while (1) infinitePrint(); +}
\ No newline at end of file diff --git a/OLD/csci4061/110920_breakout/zip/sol2.c b/OLD/csci4061/110920_breakout/zip/sol2.c new file mode 100644 index 0000000..04dad3e --- /dev/null +++ b/OLD/csci4061/110920_breakout/zip/sol2.c @@ -0,0 +1,52 @@ +/* +* Recitation Section Number: 9 +* Breakout Number: 6 +* Audrey Hebert (heber169) +* Qiyu Tian (tian0068) +* Mouhari Mouhamed (mouha003) +* Matt Strapp (strap012) +*/ + +#include <stdio.h> +#include <signal.h> +#include <unistd.h> +#include <time.h> + +// Remember the usage of sig_atomic_t in the recitation example +static volatile sig_atomic_t doneflag = 0; + +static void setdoneflag(int signo) { + doneflag = doneflag ^ 1; +} + +void infinitePrint() { + + static int count = 0; + printf("%ld: Count = %d\n", time(NULL), ++count); + sleep(1); +} + +int main() { + + // ------------------sol2.c----------------- + // setup signal handler - sigaction struct, sigemptyset, + struct sigaction act; + sigset_t sigset; + // specify action associated with SIGNT - sigaction() + act.sa_handler = setdoneflag; /* set up signal handler */ + act.sa_flags = 0; + if ((sigemptyset(&act.sa_mask) == -1) || + (sigaction(SIGINT, &act, NULL) == -1)) + { + perror("Failed to set SIGINT handler"); + return 1; + } + // You are free to modify the while loop but not the infinitePrint() + // ----------------------------------------- + + /* Print infinitely. */ + while (1) { + if (!doneflag) + infinitePrint(); + } +}
\ No newline at end of file diff --git a/OLD/csci4061/111620_breakout/program.c b/OLD/csci4061/111620_breakout/program.c new file mode 100644 index 0000000..52f67a1 --- /dev/null +++ b/OLD/csci4061/111620_breakout/program.c @@ -0,0 +1,155 @@ + +#include <stdio.h> +#include <stdlib.h> +#include <time.h> +#include <pthread.h> + +#define MATSIZE 5000 + +int mat1[MATSIZE][MATSIZE]; +int mat2[MATSIZE][MATSIZE]; + + +typedef struct argstruct { + int x_start; + int x_end; + int y_start; + int y_end; + int** res_mat; +} args_t; + +int getX_start(int i) { + return (i % 2) * MATSIZE / 2; +} +int getY_start(int i) { + return ((i < 2) ? 0 : 1) * MATSIZE / 2; +} + + +//TODO: Complete this function (to be accessed by a thread) which will +// perform matrix addition on a portion of a matrix, dictated by +// the input parameter 'args' +void * partial_matrix_add(void * args) { + int **dest; + args_t *input = (struct argstruct *) args; // params can be accessed using input pointer + dest = input->res_mat; //can be accessed as dest[][] now + + // Todo: Your code goes here (for reference checkout the pseudo code in the slides) + for (int i=input->x_start; i<input->x_end; i++) { + for (int j=input->y_start; j<input->y_end; j++) { + dest[i][j] = mat1[i][j]*mat2[i][j]; + } + } + return NULL; +} + +int main() { + // to store mulitple dispatcher threads + pthread_t m_threads[4]; + + // to store single default thread + pthread_t s_thread; + + // variable to pass values to multiple thread multiplication + args_t m_args[4]; + + //variable to pass values to single thread muliplication + args_t s_args; + + /** + * initializing matrices for sinlge and multiple matrix multiplication + */ + int i, j, k, c; + struct timeval t_multi_start, t_multi_end, t_single_start, t_single_end; + int ** res_mat_multi = malloc(MATSIZE * sizeof(int *)); + int ** res_mat_single = malloc(MATSIZE * sizeof(int *)); + for(i = 0; i < MATSIZE; i++) { + res_mat_multi[i] = malloc(MATSIZE * sizeof(int)); + res_mat_single[i] = malloc(MATSIZE * sizeof(int)); + } + + //Populate base matrices with random integers + //Initialize result matrices with -1 + for(j = 0; j < MATSIZE; j++) { + for(k = 0; k < MATSIZE; k++) { + mat1[j][k] = rand() % 1000 + 1; + mat2[j][k] = rand() % 1000 + 1; + res_mat_multi[j][k] = -1; + res_mat_single[j][k] = -1; + } + } +//Version 1 ************************************************************************** + //Measure time for multiple thread addition + gettimeofday(&t_multi_start, NULL); + + //Todo: create attribute for detached threads + //Create mulitple threads to populate res_mat_multi with the result + // of performing matrix addition mat1 + mat2 + for(i = 0; i < 4; i++) { + + int x_start = getX_start(i); + int y_start = getY_start(i); + int x_end = x_start + MATSIZE/2; + int y_end = y_start + MATSIZE/2; + m_args[i].res_mat = res_mat_multi; + //your code goes here + //Todo:Create m_agrs using x_start, x_end, y_start, y_end, and create detached threads + m_args[i].x_start = x_start; + m_args[i].x_end = x_end; + m_args[i].y_start = y_start; + m_args[i].y_end = y_end; + pthread_attr_t attr; + pthread_attr_init(&attr); + pthread_attr_setdetachstate(&attr, PTHREAD_CREATE_DETACHED); + pthread_create(&m_threads[i], &attr, partial_matrix_add, (void *) &m_args[i]); + } + + gettimeofday(&t_multi_end, NULL); +//Version 2 ************************************************************************* + + //Measure time for single thread addition + gettimeofday(&t_single_start, NULL); + + // Create single thread to populate res_mat_multi with the result + // of performing matrix addition mat1 + mat2 + + int x_start = 0; + int x_end = MATSIZE; + int y_start = 0; + int y_end = MATSIZE; + s_args.res_mat = res_mat_single; + //your code goes here + //Todo: Assign values to s_args using x_start, y_start etc. + s_args.x_start = x_start; + s_args.y_start = y_start; + s_args.x_end = x_end; + s_args.y_end = y_end; + //Todo:Create thread + pthread_create(&s_thread, NULL, partial_matrix_add, (void *) &s_args); + //Todo:join thread + pthread_join(s_thread, NULL); + gettimeofday(&t_single_end, NULL); + +// ********************************************************************************** + //Don't change anything from here + //Test to ensure that both methods produce the same result + c = 0; + for(j = 0; j < MATSIZE; j++) { + for(k = 0; k < MATSIZE; k++) { + if(res_mat_multi[j][k] == res_mat_single[j][k] && res_mat_multi[j][k] != -1) { + c++; + } + } + } + printf("Verification: %d out of %d entries matched.\n", c, MATSIZE * MATSIZE); + //Display time for each version + double time_taken; + time_taken = (t_multi_end.tv_sec - t_multi_start.tv_sec) * 1e6; + time_taken = (time_taken + (t_multi_end.tv_usec - t_multi_start.tv_usec)) * 1e-6; + printf("Time for multiple threads: %f seconds\n", time_taken); + + time_taken = (t_single_end.tv_sec - t_single_start.tv_sec) * 1e6; + time_taken = (time_taken + (t_single_end.tv_usec - t_single_start.tv_usec)) * 1e-6; + printf("Time for single thread: %f seconds\n", time_taken); + return 0; +} diff --git a/OLD/csci4061/112320_breakout/sol-condition_variables.c b/OLD/csci4061/112320_breakout/sol-condition_variables.c new file mode 100644 index 0000000..86cafb1 --- /dev/null +++ b/OLD/csci4061/112320_breakout/sol-condition_variables.c @@ -0,0 +1,128 @@ +#define NUM_ARGS 0 + +#include <stdio.h> +#include <stdlib.h> +#include <sys/types.h> +#include <sys/wait.h> +#include <sys/stat.h> +#include <unistd.h> +#include <fcntl.h> +#include <dirent.h> +#include <string.h> +#include <time.h> +#include <pthread.h> +#include <semaphore.h> +#include <sys/time.h> + +long condTotal = 0; + +struct queue { + + int vals[100]; + int index; //indicates the next available spot +}; + +struct condQueue { + + struct queue* q; + pthread_cond_t* cond; + pthread_mutex_t* mutex; +}; + + + +void insert(struct queue* q, int val) { + + q->vals[q->index] = val; + ++q->index; +} + +int delete(struct queue* q) { + + --q->index; + int val = q->vals[q->index]; + return val; +} + +// TODO: Insert code to use a condition variable. +void *condProducer(void* arg) { + + // Random delay. DO NOT REMOVE! + usleep(rand() % 1000); + + struct condQueue* cq = (struct condQueue*) arg; + + pthread_mutex_lock(cq->mutex); + + // Counter. + static int in = 0; + ++in; + + // Add an element to the queue. + insert(cq->q, in); + + pthread_cond_signal(cq->cond); //to send signal to any waiting consumer + pthread_mutex_unlock(cq->mutex); +} + +// TODO: Insert code to use a condition variable. +void *condConsumer(void* arg) { + + // Random delay. DO NOT REMOVE! + usleep(rand() % 1000); + + struct condQueue* cq = (struct condQueue*) arg; + + pthread_mutex_lock(cq->mutex); + while (cq->q->index < 1) pthread_cond_wait(cq->cond, cq->mutex);//wait if buffer is empty + + // Remove an element from the queue. + condTotal += delete(cq->q); + + pthread_mutex_unlock(cq->mutex); +} + +int main(int argc, char** argv) { + + if (argc != NUM_ARGS + 1) { + + printf("Wrong number of args, expected %d, given %d\n", NUM_ARGS, argc - 1); + exit(1); + } + + // Seed the random generator. + srand(time(NULL)); + + // Create threads. + pthread_t condPool[100]; + + struct timeval start; + gettimeofday(&start, NULL); + + // Create the cond variable controlled task queue. + struct condQueue* cq = (struct condQueue*) malloc(sizeof(struct condQueue)); + cq->q = (struct queue*) malloc(sizeof(struct queue)); + cq->q->index=0; + + // Allocate memory and initialize condition variable and mutex + cq->cond = (pthread_cond_t*) malloc(sizeof(pthread_cond_t)); + cq->mutex = (pthread_mutex_t*) malloc(sizeof(pthread_mutex_t)); + pthread_cond_init(cq->cond, NULL); + pthread_mutex_init(cq->mutex, NULL); + + // Launch them. + for (int i=0; i < 50; ++i) { + + pthread_create(&condPool[i], NULL, condProducer, (void*) cq); //start 50 producer threads + pthread_create(&condPool[50 + i], NULL, condConsumer, (void*) cq); //start 50 consumer threads + } + + for (int i=0; i < 100; ++i) pthread_join(condPool[i], NULL); //wait for all the threads to be finished + + struct timeval end; + gettimeofday(&end, NULL); + + printf("Cond Test: \nTotal of buffer = %ld\n", condTotal); + printf("Time (in us) to run = %ld\n\n", ((end.tv_sec - start.tv_sec) * 1000000) + (end.tv_usec - start.tv_usec)); + + } diff --git a/OLD/csci4061/112320_breakout/sol-semaphore.c b/OLD/csci4061/112320_breakout/sol-semaphore.c new file mode 100644 index 0000000..4af3a5b --- /dev/null +++ b/OLD/csci4061/112320_breakout/sol-semaphore.c @@ -0,0 +1,128 @@ +#define NUM_ARGS 0 + +#include <stdio.h> +#include <stdlib.h> +#include <sys/types.h> +#include <sys/wait.h> +#include <sys/stat.h> +#include <unistd.h> +#include <fcntl.h> +#include <dirent.h> +#include <string.h> +#include <time.h> +#include <pthread.h> +#include <semaphore.h> +#include<sys/time.h> + +long semTotal = 0; + +struct buffer { + + int vals[100]; + int index; +}; + +struct semBuffer { + + struct buffer* q; + sem_t* psem; + sem_t* csem; + pthread_mutex_t* mutex; +}; + +void insert(struct buffer* q, int val) { + + q->vals[q->index] = val; + ++q->index; +} + +int delete(struct buffer* q) { + + --q->index; + int val = q->vals[q->index]; + return val; +} + +// TODO: Insert code to use a semaphore. +void* semProducer(void* arg) { + + // Random delay. DO NOT REMOVE! + usleep(rand() % 1000); + + struct semBuffer* sq = (struct semBuffer*) arg; + sem_wait(sq->psem); + pthread_mutex_lock(sq->mutex); + + static int in = 0; + ++in; + // Add an element to the queue. + insert(sq->q, in); + + pthread_mutex_unlock(sq->mutex); + sem_post(sq->csem); + +} + +// TODO: Insert code to use a semaphore. +void* semConsumer(void* arg) { + + // Random delay. DO NOT REMOVE! + usleep(rand() % 1000); + + struct semBuffer* sq = (struct semBuffer*) arg; + + sem_wait(sq->csem); + pthread_mutex_lock(sq->mutex); + + // Reove an element from the queue. + semTotal += delete(sq->q); + + pthread_mutex_unlock(sq->mutex); + sem_post(sq->psem); +} + +int main(int argc, char** argv) { + + if (argc != NUM_ARGS + 1) { + + printf("Wrong number of args, expected %d, given %d\n", NUM_ARGS, argc - 1); + exit(1); + } + + // Seed the random generator. + srand(time(NULL)); + + // Create threads. + pthread_t semPool[100]; + + struct timeval start; + gettimeofday(&start, NULL); + + // Create task queue. + struct semBuffer* sq = (struct semBuffer*) malloc(sizeof(struct semBuffer)); + + sq->q = (struct buffer*) malloc(sizeof(struct buffer)); + sq->q->index=0; + sq->psem = (sem_t*) malloc(sizeof(sem_t)); + sq->csem = (sem_t*) malloc(sizeof(sem_t)); + sq->mutex = (pthread_mutex_t*) malloc(sizeof(pthread_mutex_t)); + + // TODO: Initilaize semaphores + sem_init(sq->psem, 0, 50); + sem_init(sq->csem, 0, 0); + + pthread_mutex_init(sq->mutex, NULL); + + for (int i=0; i < 50; ++i) { + + pthread_create(&semPool[i], NULL, semProducer, (void*) sq); + pthread_create(&semPool[50 + i], NULL, semConsumer, (void*) sq); + } + + for (int i=0; i < 100; ++i) pthread_join(semPool[i], NULL); + + struct timeval end; + gettimeofday(&end, NULL); + printf("Sem Test: \nTotal of buffer = %ld\n", semTotal); + printf("Time (in us) to complete = %ld\n", ((end.tv_sec - start.tv_sec) * 1000000) + (end.tv_usec - start.tv_usec)); +} diff --git a/OLD/ee4363/mp1/mp11/MIPSALU.v b/OLD/ee4363/mp1/mp11/MIPSALU.v new file mode 100644 index 0000000..096aff5 --- /dev/null +++ b/OLD/ee4363/mp1/mp11/MIPSALU.v @@ -0,0 +1,18 @@ +module MIPSALU (ALUctl, A, B, ALUOut, Zero); + input [3:0] ALUctl; + input [31:0] A,B; + output reg [31:0] ALUOut; + output Zero; + assign Zero = (ALUOut==0); + always @(ALUctl, A, B) + case (ALUctl) + 0: ALUOut <= A & B; + 1: ALUOut <= A | B; + 2: ALUOut <= A + B; + 6: ALUOut <= A - B; + 7: ALUOut <= A < B ? 1:0; + 12: ALUOut <= ~(A | B); + default: ALUOut <= 0; + endcase +endmodule + diff --git a/OLD/ee4363/mp1/mp11/MIPSAlu.vcd b/OLD/ee4363/mp1/mp11/MIPSAlu.vcd new file mode 100644 index 0000000..b81fdb8 --- /dev/null +++ b/OLD/ee4363/mp1/mp11/MIPSAlu.vcd @@ -0,0 +1,58 @@ +$date + Thu Dec 3 09:43:49 2020 +$end +$version + Icarus Verilog +$end +$timescale + 100ps +$end +$scope module test_mipsalu $end +$var wire 1 ! Zero $end +$var wire 32 " ALUOut [31:0] $end +$var reg 32 # A [31:0] $end +$var reg 4 $ ALUctl [3:0] $end +$var reg 32 % B [31:0] $end +$scope module U0 $end +$var wire 32 & A [31:0] $end +$var wire 4 ' ALUctl [3:0] $end +$var wire 32 ( B [31:0] $end +$var wire 1 ! Zero $end +$var reg 32 ) ALUOut [31:0] $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +b0 ) +b1 ( +bx ' +b1111 & +b1 % +bx $ +b1111 # +b0 " +1! +$end +#100 +0! +b1 " +b1 ) +b0 $ +b0 ' +#200 +b1111 " +b1111 ) +b1 $ +b1 ' +#300 +b10000 " +b10000 ) +b10 $ +b10 ' +#400 +b1110 " +b1110 ) +b110 $ +b110 ' +#500 diff --git a/OLD/ee4363/mp1/mp11/out b/OLD/ee4363/mp1/mp11/out new file mode 100644 index 0000000..b09d3dc --- /dev/null +++ b/OLD/ee4363/mp1/mp11/out @@ -0,0 +1,152 @@ +#! /usr/bin/vvp +:ivl_version "10.3 (stable)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision - 10; +:vpi_module "system"; +:vpi_module "vhdl_sys"; +:vpi_module "v2005_math"; +:vpi_module "va_math"; +S_0x5600cdc34d10 .scope module, "test_mipsalu" "test_mipsalu" 2 8; + .timescale -9 -10; +v0x5600cdc4a050_0 .var "A", 31 0; +v0x5600cdc4a130_0 .net "ALUOut", 31 0, v0x5600cdc49b10_0; 1 drivers +v0x5600cdc4a200_0 .var "ALUctl", 3 0; +v0x5600cdc4a300_0 .var "B", 31 0; +v0x5600cdc4a3d0_0 .net "Zero", 0 0, L_0x5600cdc5a530; 1 drivers +S_0x5600cdc34e90 .scope module, "U0" "MIPSALU" 2 19, 3 1 0, S_0x5600cdc34d10; + .timescale -9 -10; + .port_info 0 /INPUT 4 "ALUctl" + .port_info 1 /INPUT 32 "A" + .port_info 2 /INPUT 32 "B" + .port_info 3 /OUTPUT 32 "ALUOut" + .port_info 4 /OUTPUT 1 "Zero" +v0x5600cdbfd130_0 .net "A", 31 0, v0x5600cdc4a050_0; 1 drivers +v0x5600cdc49b10_0 .var "ALUOut", 31 0; +v0x5600cdc49bf0_0 .net "ALUctl", 3 0, v0x5600cdc4a200_0; 1 drivers +v0x5600cdc49ce0_0 .net "B", 31 0, v0x5600cdc4a300_0; 1 drivers +v0x5600cdc49dc0_0 .net "Zero", 0 0, L_0x5600cdc5a530; alias, 1 drivers +L_0x7f1879ed6018 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x5600cdc49ed0_0 .net/2u *"_s0", 31 0, L_0x7f1879ed6018; 1 drivers +E_0x5600cdc327b0 .event edge, v0x5600cdc49ce0_0, v0x5600cdbfd130_0, v0x5600cdc49bf0_0; +L_0x5600cdc5a530 .cmp/eq 32, v0x5600cdc49b10_0, L_0x7f1879ed6018; + .scope S_0x5600cdc34e90; +T_0 ; + %wait E_0x5600cdc327b0; + %load/vec4 v0x5600cdc49bf0_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_0.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_0.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_0.2, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_0.3, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_0.4, 6; + %dup/vec4; + %pushi/vec4 12, 0, 4; + %cmp/u; + %jmp/1 T_0.5, 6; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x5600cdc49b10_0, 0; + %jmp T_0.7; +T_0.0 ; + %load/vec4 v0x5600cdbfd130_0; + %load/vec4 v0x5600cdc49ce0_0; + %and; + %assign/vec4 v0x5600cdc49b10_0, 0; + %jmp T_0.7; +T_0.1 ; + %load/vec4 v0x5600cdbfd130_0; + %load/vec4 v0x5600cdc49ce0_0; + %or; + %assign/vec4 v0x5600cdc49b10_0, 0; + %jmp T_0.7; +T_0.2 ; + %load/vec4 v0x5600cdbfd130_0; + %load/vec4 v0x5600cdc49ce0_0; + %add; + %assign/vec4 v0x5600cdc49b10_0, 0; + %jmp T_0.7; +T_0.3 ; + %load/vec4 v0x5600cdbfd130_0; + %load/vec4 v0x5600cdc49ce0_0; + %sub; + %assign/vec4 v0x5600cdc49b10_0, 0; + %jmp T_0.7; +T_0.4 ; + %load/vec4 v0x5600cdbfd130_0; + %load/vec4 v0x5600cdc49ce0_0; + %cmp/u; + %flag_mov 8, 5; + %jmp/0 T_0.8, 8; + %pushi/vec4 1, 0, 32; + %jmp/1 T_0.9, 8; +T_0.8 ; End of true expr. + %pushi/vec4 0, 0, 32; + %jmp/0 T_0.9, 8; + ; End of false expr. + %blend; +T_0.9; + %assign/vec4 v0x5600cdc49b10_0, 0; + %jmp T_0.7; +T_0.5 ; + %load/vec4 v0x5600cdbfd130_0; + %load/vec4 v0x5600cdc49ce0_0; + %or; + %inv; + %assign/vec4 v0x5600cdc49b10_0, 0; + %jmp T_0.7; +T_0.7 ; + %pop/vec4 1; + %jmp T_0; + .thread T_0, $push; + .scope S_0x5600cdc34d10; +T_1 ; + %pushi/vec4 15, 0, 32; + %store/vec4 v0x5600cdc4a050_0, 0, 32; + %pushi/vec4 1, 0, 32; + %store/vec4 v0x5600cdc4a300_0, 0, 32; + %delay 100, 0; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x5600cdc4a200_0, 0, 4; + %delay 100, 0; + %pushi/vec4 1, 0, 4; + %store/vec4 v0x5600cdc4a200_0, 0, 4; + %delay 100, 0; + %pushi/vec4 2, 0, 4; + %store/vec4 v0x5600cdc4a200_0, 0, 4; + %delay 100, 0; + %pushi/vec4 6, 0, 4; + %store/vec4 v0x5600cdc4a200_0, 0, 4; + %delay 100, 0; + %vpi_call 2 32 "$finish" {0 0 0}; + %end; + .thread T_1; + .scope S_0x5600cdc34d10; +T_2 ; + %vpi_call 2 38 "$monitor", $time, " A = %h", v0x5600cdc4a050_0, " B = %h", v0x5600cdc4a300_0, " ALUOut = %h", v0x5600cdc4a130_0, " Zero = %b", v0x5600cdc4a3d0_0 {0 0 0}; + %end; + .thread T_2; + .scope S_0x5600cdc34d10; +T_3 ; + %vpi_call 2 43 "$dumpfile", "MIPSAlu.vcd" {0 0 0}; + %vpi_call 2 44 "$dumpvars" {0 0 0}; + %end; + .thread T_3; +# The file index is used to find the file name in the following table. +:file_names 4; + "N/A"; + "<interactive>"; + "test_mipsalu.v"; + "./MIPSALU.v"; diff --git a/OLD/ee4363/mp1/mp11/test_mipsalu.v b/OLD/ee4363/mp1/mp11/test_mipsalu.v new file mode 100644 index 0000000..9738ed5 --- /dev/null +++ b/OLD/ee4363/mp1/mp11/test_mipsalu.v @@ -0,0 +1,49 @@ + `timescale 1ns/100ps +// +// Test Bench for the mips alu +// T. Posbergh, 14 October 2012 +// + `include "MIPSALU.v" +// +module test_mipsalu; + wire Zero; // ALU bit output + wire [31:0] ALUOut; // ALU word output + reg [31:0] A,B; // ALU word inpus + reg [3:0] ALUctl; + + reg clock; + reg reset; + +// instantiate the alu and control + + MIPSALU U0(ALUctl, A, B, ALUOut, Zero); + +// generate test signals + + initial + begin + A=32'b0000_0000_0000_0000_0000_0000_0000_1111; + B=32'b0000_0000_0000_0000_0000_0000_0000_0001; + #10 ALUctl=4'b0000; + #10 ALUctl=4'b0001; + #10 ALUctl=4'b0010; + #10 ALUctl=4'b0110; +// $finish(100); + #10 $finish; + end + +// output result + + initial + $monitor($time, " A = %h",A," B = %h",B," ALUOut = %h",ALUOut," Zero = %b",Zero); + +// the following generates vcd file for GTKwave + initial + begin + $dumpfile("MIPSAlu.vcd"); + $dumpvars; + end + +endmodule + + diff --git a/OLD/ee4363/mp1/mp12/mipspipe.v b/OLD/ee4363/mp1/mp12/mipspipe.v new file mode 100644 index 0000000..41d244d --- /dev/null +++ b/OLD/ee4363/mp1/mp12/mipspipe.v @@ -0,0 +1,101 @@ +// Incomplete behavioral model of MIPS pipeline + +module mipspipe(clock); + // in_out + input clock; + + // Instruction opcodes + parameter LW = 6'b100011, SW = 6'b101011, BEQ = 6'b000100, nop = 32'b00000_100000, ALUop = 6'b0; + reg [31:0] PC, // Program counter + Regs[0:31], // Register file + IMemory[0:1023], DMemory[0:1023], // Instruction and data memories + IFIDIR, IDEXA, IDEXB, IDEXIR, EXMEMIR, EXMEMB, // pipeline latches + EXMEMALUOut, MEMWBValue, MEMWBIR; // pipeline latches + + wire [4:0] IDEXrs, IDEXrt, EXMEMrd, MEMWBrd, MEMWBrt; // fields of pipeline latches + wire [5:0] EXMEMop, MEMWBop, IDEXop; // opcodes + wire [31:0] Ain, Bin; // ALU inputs + + // Define fields of pipeline latches + assign IDEXrs = IDEXIR[25:21]; // rs field + assign IDEXrt = IDEXIR[20:16]; // rt field + assign EXMEMrd = EXMEMIR[15:11]; // rd field + assign MEMWBrd = MEMWBIR[15:11]; // rd field + assign MEMWBrt = MEMWBIR[20:16]; // rt field -- for loads + assign EXMEMop = EXMEMIR[31:26]; // opcode + assign MEMWBop = MEMWBIR[31:26]; // opcode + assign IDEXop = IDEXIR[31:26]; // opcode + + // Inputs to the ALU come directly from the ID/EX pipeline latches + assign Ain = IDEXA; + assign Bin = IDEXB; + reg [5:0] i; //used to initialize registers + reg [10:0] j,k; //used to initialize registers + + initial begin + PC = 0; + IFIDIR = nop; + IDEXIR = nop; + EXMEMIR = nop; + MEMWBIR = nop; // no-ops placed in pipeline latches + // test some instructions + for (i=0;i<=31;i=i+1) Regs[i] = i; // initialize registers + IMemory[0] = 32'h00412820; // ADD OPCODE: 000000 00010 00001 00101 00000 100000 + IMemory[1] = nop; + IMemory[2] = nop; + IMemory[3] = nop; + IMemory[4] = 32'h8CA30004; // First LW: 100011 00101 00011 00000 00000 000100 + IMemory[5] = 32'h8C420000; // Second LW: 100011 00010 00010 00000 00000 000000 + IMemory[6] = nop; + IMemory[7] = nop; + IMemory[8] = 32'h00A31825; // OR OPCODE: 000000 00101 00011 00011 00000 100101 + IMemory[9] = nop; + IMemory[10] =nop; + IMemory[11] = nop; + IMemory[12] = 32'hACA30000; // SW: 101011 00101 00011 00000 00000 000000 + for (j=13;j<=1023;j=j+1) IMemory[j] = nop; + DMemory[0] = 32'h00000000; + DMemory[1] = 32'hffffffff; + for (k=2;k<=1023;k=k+1) DMemory[k] = 0; + end + + always @ (posedge clock) + begin + // FETCH: Fetch instruction & update PC + IFIDIR <= IMemory[PC>>2]; + PC <= PC + 4; + + // DECODE: Read registers + IDEXA <= Regs[IFIDIR[25:21]]; + IDEXB <= Regs[IFIDIR[20:16]]; // get two registers + + IDEXIR <= IFIDIR; // pass along IR + + // EX: Address calculation or ALU operation + if ((IDEXop==LW) |(IDEXop==SW)) // address calculation + EXMEMALUOut <= IDEXA +{{16{IDEXIR[15]}}, IDEXIR[15:0]}; + else if (IDEXop==ALUop) begin // ALU operation + case (IDEXIR[5:0]) // R-type instruction + 32: EXMEMALUOut <= Ain + Bin; // add operation + 37: EXMEMALUOut <= Ain | Bin; //or + default: ; // other R-type operations [to be implemented] + endcase + end + + EXMEMIR <= IDEXIR; EXMEMB <= IDEXB; //pass along the IR & B + + // MEM + if (EXMEMop==ALUop) MEMWBValue <= EXMEMALUOut; //pass along ALU result + else if (EXMEMop == LW) MEMWBValue <= DMemory[EXMEMALUOut>>2]; // load + else if (EXMEMop == SW) DMemory[EXMEMALUOut>>2] <=EXMEMB; // store + + MEMWBIR <= EXMEMIR; //pass along IR + + // WB + if ((MEMWBop==ALUop) & (MEMWBrd != 0)) // update registers if ALU operation and destination not 0 + Regs[MEMWBrd] <= MEMWBValue; // ALU operation + else if ((MEMWBop == LW)& (MEMWBrt != 0)) // Update registers if load and destination not 0 + Regs[MEMWBrt] <= MEMWBValue; + end + +endmodule diff --git a/OLD/ee4363/mp1/mp12/out b/OLD/ee4363/mp1/mp12/out new file mode 100644 index 0000000..9bb25bb --- /dev/null +++ b/OLD/ee4363/mp1/mp12/out @@ -0,0 +1,401 @@ +#! /usr/bin/vvp +:ivl_version "10.3 (stable)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision + 0; +:vpi_module "system"; +:vpi_module "vhdl_sys"; +:vpi_module "v2005_math"; +:vpi_module "va_math"; +S_0x55b4011cce40 .scope module, "test_mipspipe" "test_mipspipe" 2 8; + .timescale 0 0; +v0x55b401210350_0 .var "clock", 0 0; +v0x55b4012103f0_0 .var "clock_cycle", 3 0; +E_0x55b4011e0f80 .event negedge, v0x55b40120ffb0_0; +S_0x55b4011cc9a0 .scope module, "u_mipspipe" "mipspipe" 2 14, 3 3 0, S_0x55b4011cce40; + .timescale 0 0; + .port_info 0 /INPUT 1 "clock" +P_0x55b4011cd2e0 .param/l "ALUop" 0 3 8, C4<000000>; +P_0x55b4011cd320 .param/l "BEQ" 0 3 8, C4<000100>; +P_0x55b4011cd360 .param/l "LW" 0 3 8, C4<100011>; +P_0x55b4011cd3a0 .param/l "SW" 0 3 8, C4<101011>; +P_0x55b4011cd3e0 .param/l "nop" 0 3 8, C4<00000000000000000000000000100000>; +L_0x55b4011a7a40 .functor BUFZ 32, v0x55b40120f2d0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x55b4011a7820 .functor BUFZ 32, v0x55b40120f3b0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +v0x55b4011d6de0_0 .net "Ain", 31 0, L_0x55b4011a7a40; 1 drivers +v0x55b40120eca0_0 .net "Bin", 31 0, L_0x55b4011a7820; 1 drivers +v0x55b40120ed80 .array "DMemory", 1023 0, 31 0; +v0x55b40120ee20_0 .var "EXMEMALUOut", 31 0; +v0x55b40120ef00_0 .var "EXMEMB", 31 0; +v0x55b40120f030_0 .var "EXMEMIR", 31 0; +v0x55b40120f110_0 .net "EXMEMop", 5 0, L_0x55b401210910; 1 drivers +v0x55b40120f1f0_0 .net "EXMEMrd", 4 0, L_0x55b4012105f0; 1 drivers +v0x55b40120f2d0_0 .var "IDEXA", 31 0; +v0x55b40120f3b0_0 .var "IDEXB", 31 0; +v0x55b40120f490_0 .var "IDEXIR", 31 0; +v0x55b40120f570_0 .net "IDEXop", 5 0, L_0x55b401210ae0; 1 drivers +v0x55b40120f650_0 .net "IDEXrs", 4 0, L_0x55b4012104b0; 1 drivers +v0x55b40120f730_0 .net "IDEXrt", 4 0, L_0x55b401210550; 1 drivers +v0x55b40120f810_0 .var "IFIDIR", 31 0; +v0x55b40120f8f0 .array "IMemory", 1023 0, 31 0; +v0x55b40120f9b0_0 .var "MEMWBIR", 31 0; +v0x55b40120fa90_0 .var "MEMWBValue", 31 0; +v0x55b40120fb70_0 .net "MEMWBop", 5 0, L_0x55b401210a40; 1 drivers +v0x55b40120fc50_0 .net "MEMWBrd", 4 0, L_0x55b4012106c0; 1 drivers +v0x55b40120fd30_0 .net "MEMWBrt", 4 0, L_0x55b4012107f0; 1 drivers +v0x55b40120fe10_0 .var "PC", 31 0; +v0x55b40120fef0 .array "Regs", 31 0, 31 0; +v0x55b40120ffb0_0 .net "clock", 0 0, v0x55b401210350_0; 1 drivers +v0x55b401210070_0 .var "i", 5 0; +v0x55b401210150_0 .var "j", 10 0; +v0x55b401210230_0 .var "k", 10 0; +E_0x55b4011e1270 .event posedge, v0x55b40120ffb0_0; +L_0x55b4012104b0 .part v0x55b40120f490_0, 21, 5; +L_0x55b401210550 .part v0x55b40120f490_0, 16, 5; +L_0x55b4012105f0 .part v0x55b40120f030_0, 11, 5; +L_0x55b4012106c0 .part v0x55b40120f9b0_0, 11, 5; +L_0x55b4012107f0 .part v0x55b40120f9b0_0, 16, 5; +L_0x55b401210910 .part v0x55b40120f030_0, 26, 6; +L_0x55b401210a40 .part v0x55b40120f9b0_0, 26, 6; +L_0x55b401210ae0 .part v0x55b40120f490_0, 26, 6; + .scope S_0x55b4011cc9a0; +T_0 ; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x55b40120fe10_0, 0, 32; + %pushi/vec4 32, 0, 32; + %store/vec4 v0x55b40120f810_0, 0, 32; + %pushi/vec4 32, 0, 32; + %store/vec4 v0x55b40120f490_0, 0, 32; + %pushi/vec4 32, 0, 32; + %store/vec4 v0x55b40120f030_0, 0, 32; + %pushi/vec4 32, 0, 32; + %store/vec4 v0x55b40120f9b0_0, 0, 32; + %pushi/vec4 0, 0, 6; + %store/vec4 v0x55b401210070_0, 0, 6; +T_0.0 ; + %load/vec4 v0x55b401210070_0; + %pad/u 32; + %cmpi/u 31, 0, 32; + %flag_or 5, 4; + %jmp/0xz T_0.1, 5; + %load/vec4 v0x55b401210070_0; + %pad/u 32; + %load/vec4 v0x55b401210070_0; + %pad/u 7; + %ix/vec4 4; + %store/vec4a v0x55b40120fef0, 4, 0; + %load/vec4 v0x55b401210070_0; + %addi 1, 0, 6; + %store/vec4 v0x55b401210070_0, 0, 6; + %jmp T_0.0; +T_0.1 ; + %pushi/vec4 4270112, 0, 32; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x55b40120f8f0, 4, 0; + %pushi/vec4 32, 0, 32; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x55b40120f8f0, 4, 0; + %pushi/vec4 32, 0, 32; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x55b40120f8f0, 4, 0; + %pushi/vec4 32, 0, 32; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x55b40120f8f0, 4, 0; + %pushi/vec4 2359492612, 0, 32; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x55b40120f8f0, 4, 0; + %pushi/vec4 2353135616, 0, 32; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x55b40120f8f0, 4, 0; + %pushi/vec4 32, 0, 32; + %ix/load 4, 6, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x55b40120f8f0, 4, 0; + %pushi/vec4 32, 0, 32; + %ix/load 4, 7, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x55b40120f8f0, 4, 0; + %pushi/vec4 10688549, 0, 32; + %ix/load 4, 8, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x55b40120f8f0, 4, 0; + %pushi/vec4 32, 0, 32; + %ix/load 4, 9, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x55b40120f8f0, 4, 0; + %pushi/vec4 32, 0, 32; + %ix/load 4, 10, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x55b40120f8f0, 4, 0; + %pushi/vec4 32, 0, 32; + %ix/load 4, 11, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x55b40120f8f0, 4, 0; + %pushi/vec4 2896363520, 0, 32; + %ix/load 4, 12, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x55b40120f8f0, 4, 0; + %pushi/vec4 13, 0, 11; + %store/vec4 v0x55b401210150_0, 0, 11; +T_0.2 ; + %load/vec4 v0x55b401210150_0; + %pad/u 32; + %cmpi/u 1023, 0, 32; + %flag_or 5, 4; + %jmp/0xz T_0.3, 5; + %pushi/vec4 32, 0, 32; + %load/vec4 v0x55b401210150_0; + %pad/u 12; + %ix/vec4 4; + %store/vec4a v0x55b40120f8f0, 4, 0; + %load/vec4 v0x55b401210150_0; + %addi 1, 0, 11; + %store/vec4 v0x55b401210150_0, 0, 11; + %jmp T_0.2; +T_0.3 ; + %pushi/vec4 0, 0, 32; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x55b40120ed80, 4, 0; + %pushi/vec4 4294967295, 0, 32; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x55b40120ed80, 4, 0; + %pushi/vec4 2, 0, 11; + %store/vec4 v0x55b401210230_0, 0, 11; +T_0.4 ; + %load/vec4 v0x55b401210230_0; + %pad/u 32; + %cmpi/u 1023, 0, 32; + %flag_or 5, 4; + %jmp/0xz T_0.5, 5; + %pushi/vec4 0, 0, 32; + %load/vec4 v0x55b401210230_0; + %pad/u 12; + %ix/vec4 4; + %store/vec4a v0x55b40120ed80, 4, 0; + %load/vec4 v0x55b401210230_0; + %addi 1, 0, 11; + %store/vec4 v0x55b401210230_0, 0, 11; + %jmp T_0.4; +T_0.5 ; + %end; + .thread T_0; + .scope S_0x55b4011cc9a0; +T_1 ; + %wait E_0x55b4011e1270; + %load/vec4 v0x55b40120fe10_0; + %ix/load 5, 2, 0; + %flag_set/imm 4, 0; + %shiftr 5; + %ix/vec4 4; + %load/vec4a v0x55b40120f8f0, 4; + %assign/vec4 v0x55b40120f810_0, 0; + %load/vec4 v0x55b40120fe10_0; + %addi 4, 0, 32; + %assign/vec4 v0x55b40120fe10_0, 0; + %load/vec4 v0x55b40120f810_0; + %parti/s 5, 21, 6; + %pad/u 7; + %ix/vec4 4; + %load/vec4a v0x55b40120fef0, 4; + %assign/vec4 v0x55b40120f2d0_0, 0; + %load/vec4 v0x55b40120f810_0; + %parti/s 5, 16, 6; + %pad/u 7; + %ix/vec4 4; + %load/vec4a v0x55b40120fef0, 4; + %assign/vec4 v0x55b40120f3b0_0, 0; + %load/vec4 v0x55b40120f810_0; + %assign/vec4 v0x55b40120f490_0, 0; + %load/vec4 v0x55b40120f570_0; + %pushi/vec4 35, 0, 6; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x55b40120f570_0; + %pushi/vec4 43, 0, 6; + %cmp/e; + %flag_get/vec4 4; + %or; + %flag_set/vec4 8; + %jmp/0xz T_1.0, 8; + %load/vec4 v0x55b40120f2d0_0; + %load/vec4 v0x55b40120f490_0; + %parti/s 1, 15, 5; + %replicate 16; + %load/vec4 v0x55b40120f490_0; + %parti/s 16, 0, 2; + %concat/vec4; draw_concat_vec4 + %add; + %assign/vec4 v0x55b40120ee20_0, 0; + %jmp T_1.1; +T_1.0 ; + %load/vec4 v0x55b40120f570_0; + %cmpi/e 0, 0, 6; + %jmp/0xz T_1.2, 4; + %load/vec4 v0x55b40120f490_0; + %parti/s 6, 0, 2; + %dup/vec4; + %pushi/vec4 32, 0, 6; + %cmp/u; + %jmp/1 T_1.4, 6; + %dup/vec4; + %pushi/vec4 37, 0, 6; + %cmp/u; + %jmp/1 T_1.5, 6; + %jmp T_1.7; +T_1.4 ; + %load/vec4 v0x55b4011d6de0_0; + %load/vec4 v0x55b40120eca0_0; + %add; + %assign/vec4 v0x55b40120ee20_0, 0; + %jmp T_1.7; +T_1.5 ; + %load/vec4 v0x55b4011d6de0_0; + %load/vec4 v0x55b40120eca0_0; + %or; + %assign/vec4 v0x55b40120ee20_0, 0; + %jmp T_1.7; +T_1.7 ; + %pop/vec4 1; +T_1.2 ; +T_1.1 ; + %load/vec4 v0x55b40120f490_0; + %assign/vec4 v0x55b40120f030_0, 0; + %load/vec4 v0x55b40120f3b0_0; + %assign/vec4 v0x55b40120ef00_0, 0; + %load/vec4 v0x55b40120f110_0; + %cmpi/e 0, 0, 6; + %jmp/0xz T_1.8, 4; + %load/vec4 v0x55b40120ee20_0; + %assign/vec4 v0x55b40120fa90_0, 0; + %jmp T_1.9; +T_1.8 ; + %load/vec4 v0x55b40120f110_0; + %cmpi/e 35, 0, 6; + %jmp/0xz T_1.10, 4; + %load/vec4 v0x55b40120ee20_0; + %ix/load 5, 2, 0; + %flag_set/imm 4, 0; + %shiftr 5; + %ix/vec4 4; + %load/vec4a v0x55b40120ed80, 4; + %assign/vec4 v0x55b40120fa90_0, 0; + %jmp T_1.11; +T_1.10 ; + %load/vec4 v0x55b40120f110_0; + %cmpi/e 43, 0, 6; + %jmp/0xz T_1.12, 4; + %load/vec4 v0x55b40120ef00_0; + %load/vec4 v0x55b40120ee20_0; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %shiftr 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x55b40120ed80, 0, 4; +T_1.12 ; +T_1.11 ; +T_1.9 ; + %load/vec4 v0x55b40120f030_0; + %assign/vec4 v0x55b40120f9b0_0, 0; + %load/vec4 v0x55b40120fb70_0; + %pushi/vec4 0, 0, 6; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x55b40120fc50_0; + %pad/u 32; + %pushi/vec4 0, 0, 32; + %cmp/e; + %flag_get/vec4 4; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_1.14, 8; + %load/vec4 v0x55b40120fa90_0; + %load/vec4 v0x55b40120fc50_0; + %pad/u 7; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x55b40120fef0, 0, 4; + %jmp T_1.15; +T_1.14 ; + %load/vec4 v0x55b40120fb70_0; + %pushi/vec4 35, 0, 6; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x55b40120fd30_0; + %pad/u 32; + %pushi/vec4 0, 0, 32; + %cmp/e; + %flag_get/vec4 4; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_1.16, 8; + %load/vec4 v0x55b40120fa90_0; + %load/vec4 v0x55b40120fd30_0; + %pad/u 7; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x55b40120fef0, 0, 4; +T_1.16 ; +T_1.15 ; + %jmp T_1; + .thread T_1; + .scope S_0x55b4011cce40; +T_2 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x55b401210350_0, 0, 1; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x55b4012103f0_0, 0, 4; + %delay 160, 0; + %vpi_call 2 20 "$finish" {0 0 0}; + %end; + .thread T_2; + .scope S_0x55b4011cce40; +T_3 ; + %delay 5, 0; + %load/vec4 v0x55b401210350_0; + %inv; + %store/vec4 v0x55b401210350_0, 0, 1; + %jmp T_3; + .thread T_3; + .scope S_0x55b4011cce40; +T_4 ; + %wait E_0x55b4011e1270; + %load/vec4 v0x55b4012103f0_0; + %addi 1, 0, 4; + %store/vec4 v0x55b4012103f0_0, 0, 4; + %jmp T_4; + .thread T_4; + .scope S_0x55b4011cce40; +T_5 ; + %wait E_0x55b4011e0f80; + %vpi_call 2 36 "$display", "\012\012clock cycle = %d", v0x55b4012103f0_0, " (time = %1.0t)", $time {0 0 0}; + %vpi_call 2 37 "$display", "IF/ID registers\012\011 IF/ID.PC+4 = %h, IF/ID.IR = %h \012", v0x55b40120fe10_0, v0x55b40120f810_0 {0 0 0}; + %vpi_call 2 38 "$display", "ID/EX registers\012\011 ID/EX.rs = %d, ID/EX.rt = %d", v0x55b40120f650_0, v0x55b40120f730_0, "\012\011 ID/EX.A = %h, ID/EX.B = %h", v0x55b40120f2d0_0, v0x55b40120f3b0_0 {0 0 0}; + %vpi_call 2 39 "$display", "\011 ID/EX.op = %h\012", v0x55b40120f570_0 {0 0 0}; + %vpi_call 2 40 "$display", "EX/MEM registers\012\011 EX/MEM.rs = %d, EX/MEM.rt = %d", v0x55b40120f650_0, v0x55b40120f730_0, "\012\011 EX/MEM.ALUOut = %h, EX/MEM.ALUout = %h", v0x55b40120ee20_0, v0x55b40120ef00_0 {0 0 0}; + %vpi_call 2 41 "$display", "\011 EX/MEM.op = %h\012", v0x55b40120f110_0 {0 0 0}; + %vpi_call 2 42 "$display", "MEM/WB registers\012\011 MEM/WB.rd = %d, MEM/WB.rt = %d", v0x55b40120fc50_0, v0x55b40120fd30_0, "\012\011 MEM/WB.value = %h", v0x55b40120fa90_0 {0 0 0}; + %vpi_call 2 43 "$display", "\011 EX/MEM.op = %h\012", v0x55b40120fb70_0 {0 0 0}; + %jmp T_5; + .thread T_5; + .scope S_0x55b4011cce40; +T_6 ; + %vpi_call 2 49 "$dumpfile", "test_mipspipe.vcd" {0 0 0}; + %vpi_call 2 50 "$dumpvars" {0 0 0}; + %end; + .thread T_6; +# The file index is used to find the file name in the following table. +:file_names 4; + "N/A"; + "<interactive>"; + "test_mipspipe.v"; + "./mipspipe.v"; diff --git a/OLD/ee4363/mp1/mp12/test_mipspipe.v b/OLD/ee4363/mp1/mp12/test_mipspipe.v new file mode 100644 index 0000000..24576ec --- /dev/null +++ b/OLD/ee4363/mp1/mp12/test_mipspipe.v @@ -0,0 +1,53 @@ +// +// Test bench for the mipspipe +// Boram Lee +// + +`include "mipspipe.v" + +module test_mipspipe; + + reg clock; + reg [3:0] clock_cycle; + +// instantiate pipeline module + mipspipe u_mipspipe(clock); + +// initialize clock and cycle counter + initial begin + clock = 0; + clock_cycle=4'h0; + #160 $finish; + end + +// 10 unit clock cycle + always + #5 clock = ~clock; + + always @(posedge clock) + begin + clock_cycle=clock_cycle+1; + end + + +// display contents of pipeline latches at the end of each clock cycle + always @(negedge clock) + begin + $display("\n\nclock cycle = %d",clock_cycle," (time = %1.0t)",$time); + $display("IF/ID registers\n\t IF/ID.PC+4 = %h, IF/ID.IR = %h \n", u_mipspipe.PC, u_mipspipe.IFIDIR); + $display("ID/EX registers\n\t ID/EX.rs = %d, ID/EX.rt = %d",u_mipspipe.IDEXrs,u_mipspipe.IDEXrt,"\n\t ID/EX.A = %h, ID/EX.B = %h",u_mipspipe.IDEXA,u_mipspipe.IDEXB); + $display("\t ID/EX.op = %h\n",u_mipspipe.IDEXop); + $display("EX/MEM registers\n\t EX/MEM.rs = %d, EX/MEM.rt = %d",u_mipspipe.IDEXrs,u_mipspipe.IDEXrt,"\n\t EX/MEM.ALUOut = %h, EX/MEM.ALUout = %h",u_mipspipe.EXMEMALUOut,u_mipspipe.EXMEMB); + $display("\t EX/MEM.op = %h\n",u_mipspipe.EXMEMop); + $display("MEM/WB registers\n\t MEM/WB.rd = %d, MEM/WB.rt = %d",u_mipspipe.MEMWBrd,u_mipspipe.MEMWBrt,"\n\t MEM/WB.value = %h",u_mipspipe.MEMWBValue); + $display("\t EX/MEM.op = %h\n",u_mipspipe.MEMWBop); + end + +// log to a vcd (variable change dump) file + initial + begin + $dumpfile("test_mipspipe.vcd"); + $dumpvars; + end + +endmodule diff --git a/OLD/ee4363/mp1/mp12/test_mipspipe.vcd b/OLD/ee4363/mp1/mp12/test_mipspipe.vcd new file mode 100644 index 0000000..d70b8fd --- /dev/null +++ b/OLD/ee4363/mp1/mp12/test_mipspipe.vcd @@ -0,0 +1,311 @@ +$date + Thu Dec 3 19:41:59 2020 +$end +$version + Icarus Verilog +$end +$timescale + 1s +$end +$scope module test_mipspipe $end +$var reg 1 ! clock $end +$var reg 4 " clock_cycle [3:0] $end +$scope module u_mipspipe $end +$var wire 32 # Ain [31:0] $end +$var wire 32 $ Bin [31:0] $end +$var wire 1 ! clock $end +$var wire 5 % MEMWBrt [4:0] $end +$var wire 5 & MEMWBrd [4:0] $end +$var wire 6 ' MEMWBop [5:0] $end +$var wire 5 ( IDEXrt [4:0] $end +$var wire 5 ) IDEXrs [4:0] $end +$var wire 6 * IDEXop [5:0] $end +$var wire 5 + EXMEMrd [4:0] $end +$var wire 6 , EXMEMop [5:0] $end +$var reg 32 - EXMEMALUOut [31:0] $end +$var reg 32 . EXMEMB [31:0] $end +$var reg 32 / EXMEMIR [31:0] $end +$var reg 32 0 IDEXA [31:0] $end +$var reg 32 1 IDEXB [31:0] $end +$var reg 32 2 IDEXIR [31:0] $end +$var reg 32 3 IFIDIR [31:0] $end +$var reg 32 4 MEMWBIR [31:0] $end +$var reg 32 5 MEMWBValue [31:0] $end +$var reg 32 6 PC [31:0] $end +$var reg 6 7 i [5:0] $end +$var reg 11 8 j [10:0] $end +$var reg 11 9 k [10:0] $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +b10000000000 9 +b10000000000 8 +b100000 7 +b0 6 +bx 5 +b100000 4 +b100000 3 +b100000 2 +bx 1 +bx 0 +b100000 / +bx . +bx - +b0 , +b0 + +b0 * +b0 ) +b0 ( +b0 ' +b0 & +b0 % +bx $ +bx # +b0 " +0! +$end +#5 +b0 $ +b0 1 +b0 # +b0 0 +b100 6 +b10000010010100000100000 3 +b1 " +1! +#10 +0! +#15 +b10 ) +b1 ( +b0 . +b0 - +b10000010010100000100000 2 +b1 $ +b1 1 +b10 # +b10 0 +b1000 6 +b100000 3 +b10 " +1! +#20 +0! +#25 +b101 + +b0 ) +b0 ( +b0 5 +b1 . +b10000010010100000100000 / +b11 - +b100000 2 +b0 $ +b0 1 +b0 # +b0 0 +b1100 6 +b11 " +1! +#30 +0! +#35 +b101 & +b1 % +b0 + +b10000010010100000100000 4 +b11 5 +b0 . +b100000 / +b0 - +b10000 6 +b100 " +1! +#40 +0! +#45 +b0 & +b0 % +b100000 4 +b0 5 +b10100 6 +b10001100101000110000000000000100 3 +b101 " +1! +#50 +0! +#55 +b101 ) +b11 ( +b100011 * +b10001100101000110000000000000100 2 +b11 $ +b11 1 +b11 # +b11 0 +b11000 6 +b10001100010000100000000000000000 3 +b110 " +1! +#60 +0! +#65 +b100011 , +b10 ) +b10 ( +b11 . +b10001100101000110000000000000100 / +b111 - +b10001100010000100000000000000000 2 +b10 $ +b10 1 +b10 # +b10 0 +b11100 6 +b100000 3 +b111 " +1! +#70 +0! +#75 +b11 % +b100011 ' +b0 ) +b0 ( +b0 * +b10001100101000110000000000000100 4 +b11111111111111111111111111111111 5 +b10 . +b10001100010000100000000000000000 / +b10 - +b100000 2 +b0 $ +b0 1 +b0 # +b0 0 +b100000 6 +b1000 " +1! +#80 +0! +#85 +b10 % +b0 , +b10001100010000100000000000000000 4 +b0 5 +b0 . +b100000 / +b0 - +b100100 6 +b101000110001100000100101 3 +b1001 " +1! +#90 +0! +#95 +b0 % +b0 ' +b101 ) +b11 ( +b100000 4 +b101000110001100000100101 2 +b11111111111111111111111111111111 $ +b11111111111111111111111111111111 1 +b11 # +b11 0 +b101000 6 +b100000 3 +b1010 " +1! +#100 +0! +#105 +b11 + +b0 ) +b0 ( +b11111111111111111111111111111111 . +b101000110001100000100101 / +b11111111111111111111111111111111 - +b100000 2 +b0 $ +b0 1 +b0 # +b0 0 +b101100 6 +b1011 " +1! +#110 +0! +#115 +b11 & +b11 % +b0 + +b101000110001100000100101 4 +b11111111111111111111111111111111 5 +b0 . +b100000 / +b0 - +b110000 6 +b1100 " +1! +#120 +0! +#125 +b0 & +b0 % +b100000 4 +b0 5 +b110100 6 +b10101100101000110000000000000000 3 +b1101 " +1! +#130 +0! +#135 +b101 ) +b11 ( +b101011 * +b10101100101000110000000000000000 2 +b11111111111111111111111111111111 $ +b11111111111111111111111111111111 1 +b11 # +b11 0 +b111000 6 +b100000 3 +b1110 " +1! +#140 +0! +#145 +b101011 , +b0 ) +b0 ( +b0 * +b11111111111111111111111111111111 . +b10101100101000110000000000000000 / +b11 - +b100000 2 +b0 $ +b0 1 +b0 # +b0 0 +b111100 6 +b1111 " +1! +#150 +0! +#155 +b11 % +b101011 ' +b0 , +b10101100101000110000000000000000 4 +b0 . +b100000 / +b0 - +b1000000 6 +b0 " +1! +#160 +0! diff --git a/OLD/ee4363/mp2/mipspipe_mp2.v b/OLD/ee4363/mp2/mipspipe_mp2.v new file mode 100644 index 0000000..9ea9fc2 --- /dev/null +++ b/OLD/ee4363/mp2/mipspipe_mp2.v @@ -0,0 +1,159 @@ +// Incomplete behavioral model of MIPS pipeline + +module mipspipe_mp2 (clock); + // in_out + input clock; + + // Instruction opcodes + parameter LW = 6'b100011, SW = 6'b101011, BEQ = 6'b000100, nop = 32'b00000_100000, ALUop = 6'b0; + reg [31:0] PC, Regs[0:31], IMemory[0:1023], DMemory[0:1023], // instruction and data memories + IFIDIR, IDEXA, IDEXB, IDEXIR, EXMEMIR, EXMEMB, // pipeline latches + EXMEMALUOut, MEMWBValue, MEMWBIR; + + wire [4:0] IDEXrs, IDEXrt, EXMEMrd, MEMWBrd, MEMWBrt, IFIDrt, IFIDrs; // hold register fields + wire [5:0] EXMEMop, MEMWBop, IDEXop, IFIDop; // hold opcodes + wire [31:0] Ain, Bin; // ALU inputs + + // declare the bypass signals + wire bypassAfromMEM, bypassAfromALUinWB, bypassBfromMEM, bypassBfromALUinWB, bypassAfromLWinWB, bypassBfromLWinWB, bypassIDEXAfromWB, bypassIDEXBfromWB, STALL; + + // Define fields of pipeline latches + assign IDEXrs = IDEXIR[25:21]; // rs field + assign IDEXrt = IDEXIR[20:16]; // rt field + assign EXMEMrd = EXMEMIR[15:11]; // rd field + assign MEMWBrd = MEMWBIR[15:11]; // rd field + assign MEMWBrt = MEMWBIR[20:16]; // rt field -- for loads + assign EXMEMop = EXMEMIR[31:26]; // opcode + assign MEMWBop = MEMWBIR[31:26]; // opcode + assign IDEXop = IDEXIR[31:26]; // opcode + assign IFIDrs = IFIDIR[25:21]; + assign IFIDrt = IFIDIR[20:16]; + assign IFIDop = IFIDIR[31:26]; + + + // The bypass to input A from the MEM stage for an ALU operation + assign bypassAfromMEM = (IDEXrs == EXMEMrd) & (IDEXrs!=0) & (EXMEMop==ALUop); + // The bypass to input B from the MEM stage for an ALU operation + assign bypassBfromMEM = 0; + // The bypass to input A from the WB stage for an ALU operation + assign bypassAfromALUinWB = 0; + // The bypass to input B from the WB stage for an ALU operation + assign bypassBfromALUinWB = 0; + // The bypass to input A from the WB stage for an LW operation + assign bypassAfromLWinWB = (IDEXrs == MEMWBIR[20:16]) & (IDEXrs!=0) & (MEMWBop==LW); + // The bypass to input B from the WB stage for an LW operation + assign bypassBfromLWinWB = 0; + //Stall to bypass A or B if need b (I'm not sorry) + assign bypassIDEXAfromWB = ((MEMWBIR != nop) & (IFIDIR != nop) & (IFIDrs == MEMWBrt) & (MEMWBop == LW)) | + ((MEMWBop == ALUop) & (MEMWBrd == IFIDrs)); + assign bypassIDEXBfromWB = ((MEMWBIR != nop) & (IFIDIR != nop) & (IFIDrt == MEMWBrt) & (MEMWBop == LW)) | + ((MEMWBop == ALUop) & (MEMWBrd == IFIDrt)); + // The A input to the ALU is bypassed from MEM if there is a bypass there, + // Otherwise from WB if there is a bypass there, and otherwise comes from the IDEX register + assign Ain = bypassAfromMEM? EXMEMALUOut : (bypassAfromALUinWB | bypassAfromLWinWB)? MEMWBValue : IDEXA; + + // The B input to the ALU is bypassed from MEM if there is a bypass there, + // Otherwise from WB if there is a bypass there, and otherwise comes from the IDEX register + // Ripped off of above just replacing "A" with "B" + assign Bin = bypassBfromMEM? EXMEMALUOut : (bypassBfromALUinWB | bypassBfromLWinWB)? MEMWBValue : IDEXB; + + + reg [5:0] i; // used to initialize latches + reg [10:0] j,k; // used to initialize memories + + // Make the Big Stall + assign STALL = (IDEXop == LW) && + //All of this is anded with the above (Lisp would be proud) + (((IFIDop == LW) && (IFIDrs == IDEXrt)) | + ((IFIDop == ALUop) && ((IFIDrs == IDEXrt) | (IFIDrt == IDEXrt))) | + ((IFIDop == SW) && ((IFIDrs == IDEXrt) | (IFIDrt == IDEXrt)))); + + initial begin + PC = 0; + IFIDIR = nop; + IDEXIR = nop; + EXMEMIR = nop; + MEMWBIR = nop; // no-ops in pipeline latches + + for (i = 0;i<=31;i = i+1) Regs[i] = i; // initialize latches + + IMemory[0] = 32'h00412820; // ADD $5, $2, $1 + IMemory[1] = 32'h8ca30004; // LW $3, 4($5) + IMemory[2] = 32'haca70005; // SW $7, 5($5) + // Hazard 1: ADD might not have written to $5 before SW reads from $5 (Type 2: Read after Write) + IMemory[3] = 32'h00602020; // ADD $4, $3, $0 + // Hazard 2: ADD might read $3 before LW writes to $3 (Type 3: Write after read) + IMemory[4] = 32'h01093020; // ADD $6, $8, $9 + IMemory[5] = 32'hac06000c; // SW $6, $12($0) + // Hazard 3: ADD and SW are trying to access the same register (Type 1: Write after Write) + IMemory[6] = 32'h00c05020; // ADD $10, $6, $0 + // Hazard 4: ADD reads from $6 and is written to (twice) immediately beforehand (Type 2: Read after Write) + IMemory[7] = 32'h8c0b0010; // LW $11, 32($0) + IMemory[8] = 32'h00000020; // ADD $0, $0, $0 + IMemory[9] = 32'h002b6020; // ADD $12, $1, $11 + // Hazard 5: LW might not have written to $11 before the last ADD reads from $11 (Type 2: Read after Write) + for (j=10; j<=1023; j=j+1) IMemory[j] = nop; + + DMemory[0] = 32'h00000000; + DMemory[1] = 32'hffffffff; + DMemory[2] = 32'h00000000; + DMemory[3] = 32'h00000000; + DMemory[4] = 32'hfffffffe; + for (k=5; k<=1023; k=k+1) DMemory[k] = 0; + end + + always @ (posedge clock) begin + if (~STALL) begin + // FETCH: Fetch instruction & update PC + IFIDIR <= IMemory[PC>>2]; + PC <= PC + 4; + + // DECODE: Read registers + if (~bypassIDEXAfromWB) begin + IDEXA <= Regs[IFIDIR[25:21]]; + end + else begin + IDEXA <= MEMWBValue; + end + + if (~bypassIDEXBfromWB) begin + IDEXB <= Regs[IFIDIR[20:16]]; + end + else begin + IDEXB <= MEMWBValue; + end + IDEXIR <= IFIDIR; + end + else begin //IF (STALL) + IDEXIR <= nop; + end + + // EX: Address calculation or ALU operation + if ((IDEXop==LW) |(IDEXop==SW)) // address calculation & copy B + EXMEMALUOut <= Ain +{{16{IDEXIR[15]}}, IDEXIR[15:0]}; + else if (IDEXop==ALUop) begin + case (IDEXIR[5:0]) // R-type instruction + 32: EXMEMALUOut <= Ain + Bin; // add operation + default: ; // other R-type operations: subtract, SLT, etc. + endcase + end + + EXMEMIR <= IDEXIR; + EXMEMB <= Bin; // pass along the IR & B register + + // MEM + if (EXMEMop==ALUop) MEMWBValue <= EXMEMALUOut; // pass along ALU result + else if (EXMEMop == LW) MEMWBValue <= DMemory[EXMEMALUOut>>2]; + else if (EXMEMop == SW) DMemory[EXMEMALUOut>>2] <=EXMEMB; // store + + MEMWBIR <= EXMEMIR; // pass along IR + + // WB + if ((MEMWBop==ALUop) & (MEMWBrd != 0)) // update latches if ALU operation and destination not 0 + Regs[MEMWBrd] <= MEMWBValue; // ALU operation + else if ((MEMWBop == LW)& (MEMWBrt != 0)) // Update latches if load and destination not 0 + Regs[MEMWBrt] <= MEMWBValue; + end + +endmodule + diff --git a/OLD/ee4363/mp2/out b/OLD/ee4363/mp2/out new file mode 100644 index 0000000..689fc48 --- /dev/null +++ b/OLD/ee4363/mp2/out @@ -0,0 +1,580 @@ +#! /usr/bin/vvp +:ivl_version "10.3 (stable)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision + 0; +:vpi_module "system"; +:vpi_module "vhdl_sys"; +:vpi_module "v2005_math"; +:vpi_module "va_math"; +S_0x5566537b5770 .scope module, "test_mipspipe" "test_mipspipe" 2 8; + .timescale 0 0; +v0x5566537e7d40_0 .var "clock", 0 0; +v0x5566537e7de0_0 .var "clock_cycle", 3 0; +E_0x55665379cec0 .event negedge, v0x5566537e79a0_0; +S_0x556653785590 .scope module, "u_mipspipe_mp2" "mipspipe_mp2" 2 14, 3 3 0, S_0x5566537b5770; + .timescale 0 0; + .port_info 0 /INPUT 1 "clock" +P_0x55665378c9c0 .param/l "ALUop" 0 3 8, C4<000000>; +P_0x55665378ca00 .param/l "BEQ" 0 3 8, C4<000100>; +P_0x55665378ca40 .param/l "LW" 0 3 8, C4<100011>; +P_0x55665378ca80 .param/l "SW" 0 3 8, C4<101011>; +P_0x55665378cac0 .param/l "nop" 0 3 8, C4<00000000000000000000000000100000>; +L_0x5566537934c0 .functor AND 1, L_0x5566537e88e0, L_0x5566537f8ba0, C4<1>, C4<1>; +L_0x55665375ea40 .functor AND 1, L_0x5566537934c0, L_0x5566537f8e30, C4<1>, C4<1>; +L_0x55665375e820 .functor AND 1, L_0x5566537f9190, L_0x5566537f93d0, C4<1>, C4<1>; +L_0x55665375e930 .functor AND 1, L_0x55665375e820, L_0x5566537f95e0, C4<1>, C4<1>; +L_0x5566537933f0 .functor AND 1, L_0x5566537f9330, L_0x5566537f98a0, C4<1>, C4<1>; +L_0x5566537bfe70 .functor AND 1, L_0x5566537933f0, L_0x5566537f9b30, C4<1>, C4<1>; +L_0x5566537bfee0 .functor AND 1, L_0x5566537bfe70, L_0x5566537f9d50, C4<1>, C4<1>; +L_0x5566537e8a00 .functor AND 1, L_0x5566537f9fb0, L_0x5566537fa0e0, C4<1>, C4<1>; +L_0x5566537fa3a0 .functor OR 1, L_0x5566537bfee0, L_0x5566537e8a00, C4<0>, C4<0>; +L_0x5566537fa780 .functor AND 1, L_0x5566537fa4b0, L_0x5566537fa5a0, C4<1>, C4<1>; +L_0x5566537fa990 .functor AND 1, L_0x5566537fa780, L_0x5566537fa8f0, C4<1>, C4<1>; +L_0x5566537fac90 .functor AND 1, L_0x5566537fa990, L_0x5566537faaa0, C4<1>, C4<1>; +L_0x5566537fb0b0 .functor AND 1, L_0x5566537fae10, L_0x5566537faf00, C4<1>, C4<1>; +L_0x5566537fb1c0 .functor OR 1, L_0x5566537fac90, L_0x5566537fb0b0, C4<0>, C4<0>; +L_0x7fd2876a2138 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x5566537fada0 .functor OR 1, L_0x7fd2876a2138, L_0x55665375e930, C4<0>, C4<0>; +L_0x7fd2876a2180 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7fd2876a22a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x5566537fb740 .functor OR 1, L_0x7fd2876a2180, L_0x7fd2876a22a0, C4<0>, C4<0>; +L_0x5566537fbec0 .functor AND 1, L_0x5566537fb580, L_0x5566537fbce0, C4<1>, C4<1>; +L_0x5566537fc470 .functor OR 1, L_0x5566537fc0c0, L_0x5566537fc2b0, C4<0>, C4<0>; +L_0x5566537fc580 .functor AND 1, L_0x5566537fbfd0, L_0x5566537fc470, C4<1>, C4<1>; +L_0x5566537fc690 .functor OR 1, L_0x5566537fbec0, L_0x5566537fc580, C4<0>, C4<0>; +L_0x5566537fcc60 .functor OR 1, L_0x5566537fc9b0, L_0x5566537fca50, C4<0>, C4<0>; +L_0x5566537fcd70 .functor AND 1, L_0x5566537fc4e0, L_0x5566537fcc60, C4<1>, C4<1>; +L_0x5566537fcf40 .functor OR 1, L_0x5566537fc690, L_0x5566537fcd70, C4<0>, C4<0>; +L_0x5566537fd050 .functor AND 1, L_0x5566537fba20, L_0x5566537fcf40, C4<1>, C4<1>; +L_0x5566537fd230 .functor BUFT 32, L_0x5566537fb8e0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +v0x5566537be880_0 .net "Ain", 31 0, L_0x5566537fb4e0; 1 drivers +v0x5566537b0640_0 .net "Bin", 31 0, L_0x5566537fd230; 1 drivers +v0x5566537e2160 .array "DMemory", 1023 0, 31 0; +v0x5566537e2200_0 .var "EXMEMALUOut", 31 0; +v0x5566537e22e0_0 .var "EXMEMB", 31 0; +v0x5566537e2410_0 .var "EXMEMIR", 31 0; +v0x5566537e24f0_0 .net "EXMEMop", 5 0, L_0x5566537e8300; 1 drivers +v0x5566537e25d0_0 .net "EXMEMrd", 4 0, L_0x5566537e7fe0; 1 drivers +v0x5566537e26b0_0 .var "IDEXA", 31 0; +v0x5566537e2790_0 .var "IDEXB", 31 0; +v0x5566537e2870_0 .var "IDEXIR", 31 0; +v0x5566537e2950_0 .net "IDEXop", 5 0, L_0x5566537e84d0; 1 drivers +v0x5566537e2a30_0 .net "IDEXrs", 4 0, L_0x5566537e7ea0; 1 drivers +v0x5566537e2b10_0 .net "IDEXrt", 4 0, L_0x5566537e7f40; 1 drivers +v0x5566537e2bf0_0 .var "IFIDIR", 31 0; +v0x5566537e2cd0_0 .net "IFIDop", 5 0, L_0x5566537e8840; 1 drivers +v0x5566537e2db0_0 .net "IFIDrs", 4 0, L_0x5566537e85c0; 1 drivers +v0x5566537e2e90_0 .net "IFIDrt", 4 0, L_0x5566537e86c0; 1 drivers +v0x5566537e2f70 .array "IMemory", 1023 0, 31 0; +v0x5566537e3030_0 .var "MEMWBIR", 31 0; +v0x5566537e3110_0 .var "MEMWBValue", 31 0; +v0x5566537e31f0_0 .net "MEMWBop", 5 0, L_0x5566537e8430; 1 drivers +v0x5566537e32d0_0 .net "MEMWBrd", 4 0, L_0x5566537e80b0; 1 drivers +v0x5566537e33b0_0 .net "MEMWBrt", 4 0, L_0x5566537e81e0; 1 drivers +v0x5566537e3490_0 .var "PC", 31 0; +v0x5566537e3570 .array "Regs", 31 0, 31 0; +v0x5566537e3630_0 .net "STALL", 0 0, L_0x5566537fd050; 1 drivers +v0x5566537e36f0_0 .net *"_s100", 0 0, L_0x5566537fa4b0; 1 drivers +L_0x7fd2876a2450 .functor BUFT 1, C4<00000000000000000000000000100000>, C4<0>, C4<0>, C4<0>; +v0x5566537e37b0_0 .net/2u *"_s102", 31 0, L_0x7fd2876a2450; 1 drivers +v0x5566537e3890_0 .net *"_s104", 0 0, L_0x5566537fa5a0; 1 drivers +v0x5566537e3950_0 .net *"_s106", 0 0, L_0x5566537fa780; 1 drivers +v0x5566537e3a30_0 .net *"_s108", 0 0, L_0x5566537fa8f0; 1 drivers +v0x5566537e3af0_0 .net *"_s110", 0 0, L_0x5566537fa990; 1 drivers +L_0x7fd2876a2498 .functor BUFT 1, C4<100011>, C4<0>, C4<0>, C4<0>; +v0x5566537e3bd0_0 .net/2u *"_s112", 5 0, L_0x7fd2876a2498; 1 drivers +v0x5566537e3cb0_0 .net *"_s114", 0 0, L_0x5566537faaa0; 1 drivers +v0x5566537e3d70_0 .net *"_s116", 0 0, L_0x5566537fac90; 1 drivers +L_0x7fd2876a24e0 .functor BUFT 1, C4<000000>, C4<0>, C4<0>, C4<0>; +v0x5566537e3e50_0 .net/2u *"_s118", 5 0, L_0x7fd2876a24e0; 1 drivers +v0x5566537e3f30_0 .net *"_s120", 0 0, L_0x5566537fae10; 1 drivers +v0x5566537e3ff0_0 .net *"_s122", 0 0, L_0x5566537faf00; 1 drivers +v0x5566537e40b0_0 .net *"_s124", 0 0, L_0x5566537fb0b0; 1 drivers +v0x5566537e4190_0 .net *"_s128", 0 0, L_0x5566537fada0; 1 drivers +v0x5566537e4270_0 .net *"_s130", 31 0, L_0x5566537fb3f0; 1 drivers +v0x5566537e4350_0 .net *"_s134", 0 0, L_0x5566537fb740; 1 drivers +v0x5566537e4430_0 .net *"_s136", 31 0, L_0x5566537fb8e0; 1 drivers +L_0x7fd2876a2528 .functor BUFT 1, C4<100011>, C4<0>, C4<0>, C4<0>; +v0x5566537e4510_0 .net/2u *"_s140", 5 0, L_0x7fd2876a2528; 1 drivers +v0x5566537e45f0_0 .net *"_s142", 0 0, L_0x5566537fba20; 1 drivers +L_0x7fd2876a2570 .functor BUFT 1, C4<100011>, C4<0>, C4<0>, C4<0>; +v0x5566537e46b0_0 .net/2u *"_s144", 5 0, L_0x7fd2876a2570; 1 drivers +v0x5566537e4790_0 .net *"_s146", 0 0, L_0x5566537fb580; 1 drivers +v0x5566537e4850_0 .net *"_s148", 0 0, L_0x5566537fbce0; 1 drivers +v0x5566537e4910_0 .net *"_s150", 0 0, L_0x5566537fbec0; 1 drivers +L_0x7fd2876a25b8 .functor BUFT 1, C4<000000>, C4<0>, C4<0>, C4<0>; +v0x5566537e49d0_0 .net/2u *"_s152", 5 0, L_0x7fd2876a25b8; 1 drivers +v0x5566537e4ab0_0 .net *"_s154", 0 0, L_0x5566537fbfd0; 1 drivers +v0x5566537e4b70_0 .net *"_s156", 0 0, L_0x5566537fc0c0; 1 drivers +v0x5566537e4c30_0 .net *"_s158", 0 0, L_0x5566537fc2b0; 1 drivers +v0x5566537e4cf0_0 .net *"_s160", 0 0, L_0x5566537fc470; 1 drivers +v0x5566537e4dd0_0 .net *"_s162", 0 0, L_0x5566537fc580; 1 drivers +v0x5566537e4e90_0 .net *"_s164", 0 0, L_0x5566537fc690; 1 drivers +L_0x7fd2876a2600 .functor BUFT 1, C4<101011>, C4<0>, C4<0>, C4<0>; +v0x5566537e4f70_0 .net/2u *"_s166", 5 0, L_0x7fd2876a2600; 1 drivers +v0x5566537e5050_0 .net *"_s168", 0 0, L_0x5566537fc4e0; 1 drivers +v0x5566537e5110_0 .net *"_s170", 0 0, L_0x5566537fc9b0; 1 drivers +v0x5566537e51d0_0 .net *"_s172", 0 0, L_0x5566537fca50; 1 drivers +v0x5566537e5290_0 .net *"_s174", 0 0, L_0x5566537fcc60; 1 drivers +v0x5566537e5370_0 .net *"_s176", 0 0, L_0x5566537fcd70; 1 drivers +v0x5566537e5430_0 .net *"_s178", 0 0, L_0x5566537fcf40; 1 drivers +v0x5566537e5510_0 .net *"_s22", 0 0, L_0x5566537e88e0; 1 drivers +v0x5566537e59e0_0 .net *"_s24", 31 0, L_0x5566537e8a70; 1 drivers +L_0x7fd2876a2018 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x5566537e5ac0_0 .net *"_s27", 26 0, L_0x7fd2876a2018; 1 drivers +L_0x7fd2876a2060 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x5566537e5ba0_0 .net/2u *"_s28", 31 0, L_0x7fd2876a2060; 1 drivers +v0x5566537e5c80_0 .net *"_s30", 0 0, L_0x5566537f8ba0; 1 drivers +v0x5566537e5d40_0 .net *"_s32", 0 0, L_0x5566537934c0; 1 drivers +L_0x7fd2876a20a8 .functor BUFT 1, C4<000000>, C4<0>, C4<0>, C4<0>; +v0x5566537e5e20_0 .net/2u *"_s34", 5 0, L_0x7fd2876a20a8; 1 drivers +v0x5566537e5f00_0 .net *"_s36", 0 0, L_0x5566537f8e30; 1 drivers +v0x5566537e5fc0_0 .net *"_s47", 4 0, L_0x5566537f9060; 1 drivers +v0x5566537e60a0_0 .net *"_s48", 0 0, L_0x5566537f9190; 1 drivers +v0x5566537e6160_0 .net *"_s50", 31 0, L_0x5566537f9260; 1 drivers +L_0x7fd2876a21c8 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x5566537e6240_0 .net *"_s53", 26 0, L_0x7fd2876a21c8; 1 drivers +L_0x7fd2876a2210 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x5566537e6320_0 .net/2u *"_s54", 31 0, L_0x7fd2876a2210; 1 drivers +v0x5566537e6400_0 .net *"_s56", 0 0, L_0x5566537f93d0; 1 drivers +v0x5566537e64c0_0 .net *"_s58", 0 0, L_0x55665375e820; 1 drivers +L_0x7fd2876a2258 .functor BUFT 1, C4<100011>, C4<0>, C4<0>, C4<0>; +v0x5566537e65a0_0 .net/2u *"_s60", 5 0, L_0x7fd2876a2258; 1 drivers +v0x5566537e6680_0 .net *"_s62", 0 0, L_0x5566537f95e0; 1 drivers +L_0x7fd2876a22e8 .functor BUFT 1, C4<00000000000000000000000000100000>, C4<0>, C4<0>, C4<0>; +v0x5566537e6740_0 .net/2u *"_s68", 31 0, L_0x7fd2876a22e8; 1 drivers +v0x5566537e6820_0 .net *"_s70", 0 0, L_0x5566537f9330; 1 drivers +L_0x7fd2876a2330 .functor BUFT 1, C4<00000000000000000000000000100000>, C4<0>, C4<0>, C4<0>; +v0x5566537e68e0_0 .net/2u *"_s72", 31 0, L_0x7fd2876a2330; 1 drivers +v0x5566537e69c0_0 .net *"_s74", 0 0, L_0x5566537f98a0; 1 drivers +v0x5566537e6a80_0 .net *"_s76", 0 0, L_0x5566537933f0; 1 drivers +v0x5566537e6b60_0 .net *"_s78", 0 0, L_0x5566537f9b30; 1 drivers +v0x5566537e6c20_0 .net *"_s80", 0 0, L_0x5566537bfe70; 1 drivers +L_0x7fd2876a2378 .functor BUFT 1, C4<100011>, C4<0>, C4<0>, C4<0>; +v0x5566537e6d00_0 .net/2u *"_s82", 5 0, L_0x7fd2876a2378; 1 drivers +v0x5566537e6de0_0 .net *"_s84", 0 0, L_0x5566537f9d50; 1 drivers +v0x5566537e6ea0_0 .net *"_s86", 0 0, L_0x5566537bfee0; 1 drivers +L_0x7fd2876a23c0 .functor BUFT 1, C4<000000>, C4<0>, C4<0>, C4<0>; +v0x5566537e6f80_0 .net/2u *"_s88", 5 0, L_0x7fd2876a23c0; 1 drivers +v0x5566537e7060_0 .net *"_s90", 0 0, L_0x5566537f9fb0; 1 drivers +v0x5566537e7120_0 .net *"_s92", 0 0, L_0x5566537fa0e0; 1 drivers +v0x5566537e71e0_0 .net *"_s94", 0 0, L_0x5566537e8a00; 1 drivers +L_0x7fd2876a2408 .functor BUFT 1, C4<00000000000000000000000000100000>, C4<0>, C4<0>, C4<0>; +v0x5566537e72c0_0 .net/2u *"_s98", 31 0, L_0x7fd2876a2408; 1 drivers +v0x5566537e73a0_0 .net "bypassAfromALUinWB", 0 0, L_0x7fd2876a2138; 1 drivers +v0x5566537e7460_0 .net "bypassAfromLWinWB", 0 0, L_0x55665375e930; 1 drivers +v0x5566537e7520_0 .net "bypassAfromMEM", 0 0, L_0x55665375ea40; 1 drivers +v0x5566537e75e0_0 .net "bypassBfromALUinWB", 0 0, L_0x7fd2876a2180; 1 drivers +v0x5566537e76a0_0 .net "bypassBfromLWinWB", 0 0, L_0x7fd2876a22a0; 1 drivers +L_0x7fd2876a20f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x5566537e7760_0 .net "bypassBfromMEM", 0 0, L_0x7fd2876a20f0; 1 drivers +v0x5566537e7820_0 .net "bypassIDEXAfromWB", 0 0, L_0x5566537fa3a0; 1 drivers +v0x5566537e78e0_0 .net "bypassIDEXBfromWB", 0 0, L_0x5566537fb1c0; 1 drivers +v0x5566537e79a0_0 .net "clock", 0 0, v0x5566537e7d40_0; 1 drivers +v0x5566537e7a60_0 .var "i", 5 0; +v0x5566537e7b40_0 .var "j", 10 0; +v0x5566537e7c20_0 .var "k", 10 0; +E_0x55665379d1b0 .event posedge, v0x5566537e79a0_0; +L_0x5566537e7ea0 .part v0x5566537e2870_0, 21, 5; +L_0x5566537e7f40 .part v0x5566537e2870_0, 16, 5; +L_0x5566537e7fe0 .part v0x5566537e2410_0, 11, 5; +L_0x5566537e80b0 .part v0x5566537e3030_0, 11, 5; +L_0x5566537e81e0 .part v0x5566537e3030_0, 16, 5; +L_0x5566537e8300 .part v0x5566537e2410_0, 26, 6; +L_0x5566537e8430 .part v0x5566537e3030_0, 26, 6; +L_0x5566537e84d0 .part v0x5566537e2870_0, 26, 6; +L_0x5566537e85c0 .part v0x5566537e2bf0_0, 21, 5; +L_0x5566537e86c0 .part v0x5566537e2bf0_0, 16, 5; +L_0x5566537e8840 .part v0x5566537e2bf0_0, 26, 6; +L_0x5566537e88e0 .cmp/eq 5, L_0x5566537e7ea0, L_0x5566537e7fe0; +L_0x5566537e8a70 .concat [ 5 27 0 0], L_0x5566537e7ea0, L_0x7fd2876a2018; +L_0x5566537f8ba0 .cmp/ne 32, L_0x5566537e8a70, L_0x7fd2876a2060; +L_0x5566537f8e30 .cmp/eq 6, L_0x5566537e8300, L_0x7fd2876a20a8; +L_0x5566537f9060 .part v0x5566537e3030_0, 16, 5; +L_0x5566537f9190 .cmp/eq 5, L_0x5566537e7ea0, L_0x5566537f9060; +L_0x5566537f9260 .concat [ 5 27 0 0], L_0x5566537e7ea0, L_0x7fd2876a21c8; +L_0x5566537f93d0 .cmp/ne 32, L_0x5566537f9260, L_0x7fd2876a2210; +L_0x5566537f95e0 .cmp/eq 6, L_0x5566537e8430, L_0x7fd2876a2258; +L_0x5566537f9330 .cmp/ne 32, v0x5566537e3030_0, L_0x7fd2876a22e8; +L_0x5566537f98a0 .cmp/ne 32, v0x5566537e2bf0_0, L_0x7fd2876a2330; +L_0x5566537f9b30 .cmp/eq 5, L_0x5566537e85c0, L_0x5566537e81e0; +L_0x5566537f9d50 .cmp/eq 6, L_0x5566537e8430, L_0x7fd2876a2378; +L_0x5566537f9fb0 .cmp/eq 6, L_0x5566537e8430, L_0x7fd2876a23c0; +L_0x5566537fa0e0 .cmp/eq 5, L_0x5566537e80b0, L_0x5566537e85c0; +L_0x5566537fa4b0 .cmp/ne 32, v0x5566537e3030_0, L_0x7fd2876a2408; +L_0x5566537fa5a0 .cmp/ne 32, v0x5566537e2bf0_0, L_0x7fd2876a2450; +L_0x5566537fa8f0 .cmp/eq 5, L_0x5566537e86c0, L_0x5566537e81e0; +L_0x5566537faaa0 .cmp/eq 6, L_0x5566537e8430, L_0x7fd2876a2498; +L_0x5566537fae10 .cmp/eq 6, L_0x5566537e8430, L_0x7fd2876a24e0; +L_0x5566537faf00 .cmp/eq 5, L_0x5566537e80b0, L_0x5566537e86c0; +L_0x5566537fb3f0 .functor MUXZ 32, v0x5566537e26b0_0, v0x5566537e3110_0, L_0x5566537fada0, C4<>; +L_0x5566537fb4e0 .functor MUXZ 32, L_0x5566537fb3f0, v0x5566537e2200_0, L_0x55665375ea40, C4<>; +L_0x5566537fb8e0 .functor MUXZ 32, v0x5566537e2790_0, v0x5566537e3110_0, L_0x5566537fb740, C4<>; +L_0x5566537fba20 .cmp/eq 6, L_0x5566537e84d0, L_0x7fd2876a2528; +L_0x5566537fb580 .cmp/eq 6, L_0x5566537e8840, L_0x7fd2876a2570; +L_0x5566537fbce0 .cmp/eq 5, L_0x5566537e85c0, L_0x5566537e7f40; +L_0x5566537fbfd0 .cmp/eq 6, L_0x5566537e8840, L_0x7fd2876a25b8; +L_0x5566537fc0c0 .cmp/eq 5, L_0x5566537e85c0, L_0x5566537e7f40; +L_0x5566537fc2b0 .cmp/eq 5, L_0x5566537e86c0, L_0x5566537e7f40; +L_0x5566537fc4e0 .cmp/eq 6, L_0x5566537e8840, L_0x7fd2876a2600; +L_0x5566537fc9b0 .cmp/eq 5, L_0x5566537e85c0, L_0x5566537e7f40; +L_0x5566537fca50 .cmp/eq 5, L_0x5566537e86c0, L_0x5566537e7f40; + .scope S_0x556653785590; +T_0 ; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x5566537e3490_0, 0, 32; + %pushi/vec4 32, 0, 32; + %store/vec4 v0x5566537e2bf0_0, 0, 32; + %pushi/vec4 32, 0, 32; + %store/vec4 v0x5566537e2870_0, 0, 32; + %pushi/vec4 32, 0, 32; + %store/vec4 v0x5566537e2410_0, 0, 32; + %pushi/vec4 32, 0, 32; + %store/vec4 v0x5566537e3030_0, 0, 32; + %pushi/vec4 0, 0, 6; + %store/vec4 v0x5566537e7a60_0, 0, 6; +T_0.0 ; + %load/vec4 v0x5566537e7a60_0; + %pad/u 32; + %cmpi/u 31, 0, 32; + %flag_or 5, 4; + %jmp/0xz T_0.1, 5; + %load/vec4 v0x5566537e7a60_0; + %pad/u 32; + %load/vec4 v0x5566537e7a60_0; + %pad/u 7; + %ix/vec4 4; + %store/vec4a v0x5566537e3570, 4, 0; + %load/vec4 v0x5566537e7a60_0; + %addi 1, 0, 6; + %store/vec4 v0x5566537e7a60_0, 0, 6; + %jmp T_0.0; +T_0.1 ; + %pushi/vec4 4270112, 0, 32; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x5566537e2f70, 4, 0; + %pushi/vec4 2359492612, 0, 32; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x5566537e2f70, 4, 0; + %pushi/vec4 2896625669, 0, 32; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x5566537e2f70, 4, 0; + %pushi/vec4 6299680, 0, 32; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x5566537e2f70, 4, 0; + %pushi/vec4 17379360, 0, 32; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x5566537e2f70, 4, 0; + %pushi/vec4 2886074380, 0, 32; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x5566537e2f70, 4, 0; + %pushi/vec4 12603424, 0, 32; + %ix/load 4, 6, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x5566537e2f70, 4, 0; + %pushi/vec4 2349531152, 0, 32; + %ix/load 4, 7, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x5566537e2f70, 4, 0; + %pushi/vec4 32, 0, 32; + %ix/load 4, 8, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x5566537e2f70, 4, 0; + %pushi/vec4 2842656, 0, 32; + %ix/load 4, 9, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x5566537e2f70, 4, 0; + %pushi/vec4 10, 0, 11; + %store/vec4 v0x5566537e7b40_0, 0, 11; +T_0.2 ; + %load/vec4 v0x5566537e7b40_0; + %pad/u 32; + %cmpi/u 1023, 0, 32; + %flag_or 5, 4; + %jmp/0xz T_0.3, 5; + %pushi/vec4 32, 0, 32; + %load/vec4 v0x5566537e7b40_0; + %pad/u 12; + %ix/vec4 4; + %store/vec4a v0x5566537e2f70, 4, 0; + %load/vec4 v0x5566537e7b40_0; + %addi 1, 0, 11; + %store/vec4 v0x5566537e7b40_0, 0, 11; + %jmp T_0.2; +T_0.3 ; + %pushi/vec4 0, 0, 32; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x5566537e2160, 4, 0; + %pushi/vec4 4294967295, 0, 32; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x5566537e2160, 4, 0; + %pushi/vec4 0, 0, 32; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x5566537e2160, 4, 0; + %pushi/vec4 0, 0, 32; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x5566537e2160, 4, 0; + %pushi/vec4 4294967294, 0, 32; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x5566537e2160, 4, 0; + %pushi/vec4 5, 0, 11; + %store/vec4 v0x5566537e7c20_0, 0, 11; +T_0.4 ; + %load/vec4 v0x5566537e7c20_0; + %pad/u 32; + %cmpi/u 1023, 0, 32; + %flag_or 5, 4; + %jmp/0xz T_0.5, 5; + %pushi/vec4 0, 0, 32; + %load/vec4 v0x5566537e7c20_0; + %pad/u 12; + %ix/vec4 4; + %store/vec4a v0x5566537e2160, 4, 0; + %load/vec4 v0x5566537e7c20_0; + %addi 1, 0, 11; + %store/vec4 v0x5566537e7c20_0, 0, 11; + %jmp T_0.4; +T_0.5 ; + %end; + .thread T_0; + .scope S_0x556653785590; +T_1 ; + %wait E_0x55665379d1b0; + %load/vec4 v0x5566537e3630_0; + %inv; + %flag_set/vec4 8; + %jmp/0xz T_1.0, 8; + %load/vec4 v0x5566537e3490_0; + %ix/load 5, 2, 0; + %flag_set/imm 4, 0; + %shiftr 5; + %ix/vec4 4; + %load/vec4a v0x5566537e2f70, 4; + %assign/vec4 v0x5566537e2bf0_0, 0; + %load/vec4 v0x5566537e3490_0; + %addi 4, 0, 32; + %assign/vec4 v0x5566537e3490_0, 0; + %load/vec4 v0x5566537e7820_0; + %inv; + %flag_set/vec4 8; + %jmp/0xz T_1.2, 8; + %load/vec4 v0x5566537e2bf0_0; + %parti/s 5, 21, 6; + %pad/u 7; + %ix/vec4 4; + %load/vec4a v0x5566537e3570, 4; + %assign/vec4 v0x5566537e26b0_0, 0; + %jmp T_1.3; +T_1.2 ; + %load/vec4 v0x5566537e3110_0; + %assign/vec4 v0x5566537e26b0_0, 0; +T_1.3 ; + %load/vec4 v0x5566537e78e0_0; + %inv; + %flag_set/vec4 8; + %jmp/0xz T_1.4, 8; + %load/vec4 v0x5566537e2bf0_0; + %parti/s 5, 16, 6; + %pad/u 7; + %ix/vec4 4; + %load/vec4a v0x5566537e3570, 4; + %assign/vec4 v0x5566537e2790_0, 0; + %jmp T_1.5; +T_1.4 ; + %load/vec4 v0x5566537e3110_0; + %assign/vec4 v0x5566537e2790_0, 0; +T_1.5 ; + %load/vec4 v0x5566537e2bf0_0; + %assign/vec4 v0x5566537e2870_0, 0; + %jmp T_1.1; +T_1.0 ; + %pushi/vec4 32, 0, 32; + %assign/vec4 v0x5566537e2870_0, 0; +T_1.1 ; + %load/vec4 v0x5566537e2950_0; + %pushi/vec4 35, 0, 6; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x5566537e2950_0; + %pushi/vec4 43, 0, 6; + %cmp/e; + %flag_get/vec4 4; + %or; + %flag_set/vec4 8; + %jmp/0xz T_1.6, 8; + %load/vec4 v0x5566537be880_0; + %load/vec4 v0x5566537e2870_0; + %parti/s 1, 15, 5; + %replicate 16; + %load/vec4 v0x5566537e2870_0; + %parti/s 16, 0, 2; + %concat/vec4; draw_concat_vec4 + %add; + %assign/vec4 v0x5566537e2200_0, 0; + %jmp T_1.7; +T_1.6 ; + %load/vec4 v0x5566537e2950_0; + %cmpi/e 0, 0, 6; + %jmp/0xz T_1.8, 4; + %load/vec4 v0x5566537e2870_0; + %parti/s 6, 0, 2; + %dup/vec4; + %pushi/vec4 32, 0, 6; + %cmp/u; + %jmp/1 T_1.10, 6; + %jmp T_1.12; +T_1.10 ; + %load/vec4 v0x5566537be880_0; + %load/vec4 v0x5566537b0640_0; + %add; + %assign/vec4 v0x5566537e2200_0, 0; + %jmp T_1.12; +T_1.12 ; + %pop/vec4 1; +T_1.8 ; +T_1.7 ; + %load/vec4 v0x5566537e2870_0; + %assign/vec4 v0x5566537e2410_0, 0; + %load/vec4 v0x5566537b0640_0; + %assign/vec4 v0x5566537e22e0_0, 0; + %load/vec4 v0x5566537e24f0_0; + %cmpi/e 0, 0, 6; + %jmp/0xz T_1.13, 4; + %load/vec4 v0x5566537e2200_0; + %assign/vec4 v0x5566537e3110_0, 0; + %jmp T_1.14; +T_1.13 ; + %load/vec4 v0x5566537e24f0_0; + %cmpi/e 35, 0, 6; + %jmp/0xz T_1.15, 4; + %load/vec4 v0x5566537e2200_0; + %ix/load 5, 2, 0; + %flag_set/imm 4, 0; + %shiftr 5; + %ix/vec4 4; + %load/vec4a v0x5566537e2160, 4; + %assign/vec4 v0x5566537e3110_0, 0; + %jmp T_1.16; +T_1.15 ; + %load/vec4 v0x5566537e24f0_0; + %cmpi/e 43, 0, 6; + %jmp/0xz T_1.17, 4; + %load/vec4 v0x5566537e22e0_0; + %load/vec4 v0x5566537e2200_0; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %shiftr 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x5566537e2160, 0, 4; +T_1.17 ; +T_1.16 ; +T_1.14 ; + %load/vec4 v0x5566537e2410_0; + %assign/vec4 v0x5566537e3030_0, 0; + %load/vec4 v0x5566537e31f0_0; + %pushi/vec4 0, 0, 6; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x5566537e32d0_0; + %pad/u 32; + %pushi/vec4 0, 0, 32; + %cmp/e; + %flag_get/vec4 4; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_1.19, 8; + %load/vec4 v0x5566537e3110_0; + %load/vec4 v0x5566537e32d0_0; + %pad/u 7; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x5566537e3570, 0, 4; + %jmp T_1.20; +T_1.19 ; + %load/vec4 v0x5566537e31f0_0; + %pushi/vec4 35, 0, 6; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x5566537e33b0_0; + %pad/u 32; + %pushi/vec4 0, 0, 32; + %cmp/e; + %flag_get/vec4 4; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_1.21, 8; + %load/vec4 v0x5566537e3110_0; + %load/vec4 v0x5566537e33b0_0; + %pad/u 7; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x5566537e3570, 0, 4; +T_1.21 ; +T_1.20 ; + %jmp T_1; + .thread T_1; + .scope S_0x5566537b5770; +T_2 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x5566537e7d40_0, 0, 1; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x5566537e7de0_0, 0, 4; + %delay 160, 0; + %vpi_call 2 20 "$finish" {0 0 0}; + %end; + .thread T_2; + .scope S_0x5566537b5770; +T_3 ; + %delay 5, 0; + %load/vec4 v0x5566537e7d40_0; + %inv; + %store/vec4 v0x5566537e7d40_0, 0, 1; + %jmp T_3; + .thread T_3; + .scope S_0x5566537b5770; +T_4 ; + %wait E_0x55665379d1b0; + %load/vec4 v0x5566537e7de0_0; + %addi 1, 0, 4; + %store/vec4 v0x5566537e7de0_0, 0, 4; + %jmp T_4; + .thread T_4; + .scope S_0x5566537b5770; +T_5 ; + %wait E_0x55665379cec0; + %vpi_call 2 36 "$display", "\012\012clock cycle = %d", v0x5566537e7de0_0, " (time = %1.0t)", $time {0 0 0}; + %vpi_call 2 37 "$display", "IF/ID registers\012\011 IF/ID.PC+4 = %h, IF/ID.IR = %h \012", v0x5566537e3490_0, v0x5566537e2bf0_0 {0 0 0}; + %vpi_call 2 38 "$display", "ID/EX registers\012\011 ID/EX.rs = %d, ID/EX.rt = %d", v0x5566537e2a30_0, v0x5566537e2b10_0, "\012\011 ID/EX.A = %h, ID/EX.B = %h", v0x5566537e26b0_0, v0x5566537e2790_0 {0 0 0}; + %vpi_call 2 39 "$display", "\011 ID/EX.op = %h\012", v0x5566537e2950_0 {0 0 0}; + %vpi_call 2 40 "$display", "EX/MEM registers\012\011 EX/MEM.rs = %d, EX/MEM.rt = %d", v0x5566537e2a30_0, v0x5566537e2b10_0, "\012\011 EX/MEM.ALUOut = %h, EX/MEM.ALUout = %h", v0x5566537e2200_0, v0x5566537e22e0_0 {0 0 0}; + %vpi_call 2 41 "$display", "\011 EX/MEM.op = %h\012", v0x5566537e24f0_0 {0 0 0}; + %vpi_call 2 42 "$display", "MEM/WB registers\012\011 MEM/WB.rd = %d, MEM/WB.rt = %d", v0x5566537e32d0_0, v0x5566537e33b0_0, "\012\011 MEM/WB.value = %h", v0x5566537e3110_0 {0 0 0}; + %vpi_call 2 43 "$display", "\011 EX/MEM.op = %h\012", v0x5566537e31f0_0 {0 0 0}; + %jmp T_5; + .thread T_5; + .scope S_0x5566537b5770; +T_6 ; + %vpi_call 2 49 "$dumpfile", "test_mipspipe.vcd" {0 0 0}; + %vpi_call 2 50 "$dumpvars" {0 0 0}; + %end; + .thread T_6; +# The file index is used to find the file name in the following table. +:file_names 4; + "N/A"; + "<interactive>"; + "test_mipspipe_mp2.v"; + "./mipspipe_mp2.v"; diff --git a/OLD/ee4363/mp2/output.txt b/OLD/ee4363/mp2/output.txt new file mode 100644 index 0000000..cefb5c6 --- /dev/null +++ b/OLD/ee4363/mp2/output.txt @@ -0,0 +1,319 @@ +VCD info: dumpfile test_mipspipe.vcd opened for output. + + +clock cycle = 1 (time = 10) +IF/ID registers + IF/ID.PC+4 = 00000004, IF/ID.IR = 00412820 + +ID/EX registers + ID/EX.rs = 0, ID/EX.rt = 0 + ID/EX.A = xxxxxxxx, ID/EX.B = xxxxxxxx + ID/EX.op = 00 + +EX/MEM registers + EX/MEM.rs = 0, EX/MEM.rt = 0 + EX/MEM.ALUOut = xxxxxxxx, EX/MEM.ALUout = xxxxxxxx + EX/MEM.op = 00 + +MEM/WB registers + MEM/WB.rd = 0, MEM/WB.rt = 0 + MEM/WB.value = xxxxxxxx + EX/MEM.op = 00 + + + +clock cycle = 2 (time = 20) +IF/ID registers + IF/ID.PC+4 = 00000008, IF/ID.IR = 8ca30004 + +ID/EX registers + ID/EX.rs = 2, ID/EX.rt = 1 + ID/EX.A = 00000002, ID/EX.B = 00000001 + ID/EX.op = 00 + +EX/MEM registers + EX/MEM.rs = 2, EX/MEM.rt = 1 + EX/MEM.ALUOut = xxxxxxxx, EX/MEM.ALUout = xxxxxxxx + EX/MEM.op = 00 + +MEM/WB registers + MEM/WB.rd = 0, MEM/WB.rt = 0 + MEM/WB.value = xxxxxxxx + EX/MEM.op = 00 + + + +clock cycle = 3 (time = 30) +IF/ID registers + IF/ID.PC+4 = 0000000c, IF/ID.IR = aca70005 + +ID/EX registers + ID/EX.rs = 5, ID/EX.rt = 3 + ID/EX.A = 00000005, ID/EX.B = 00000003 + ID/EX.op = 23 + +EX/MEM registers + EX/MEM.rs = 5, EX/MEM.rt = 3 + EX/MEM.ALUOut = 00000003, EX/MEM.ALUout = 00000001 + EX/MEM.op = 00 + +MEM/WB registers + MEM/WB.rd = 0, MEM/WB.rt = 0 + MEM/WB.value = xxxxxxxx + EX/MEM.op = 00 + + + +clock cycle = 4 (time = 40) +IF/ID registers + IF/ID.PC+4 = 00000010, IF/ID.IR = 00602020 + +ID/EX registers + ID/EX.rs = 5, ID/EX.rt = 7 + ID/EX.A = 00000005, ID/EX.B = 00000007 + ID/EX.op = 2b + +EX/MEM registers + EX/MEM.rs = 5, EX/MEM.rt = 7 + EX/MEM.ALUOut = 00000007, EX/MEM.ALUout = 00000003 + EX/MEM.op = 23 + +MEM/WB registers + MEM/WB.rd = 5, MEM/WB.rt = 1 + MEM/WB.value = 00000003 + EX/MEM.op = 00 + + + +clock cycle = 5 (time = 50) +IF/ID registers + IF/ID.PC+4 = 00000014, IF/ID.IR = 01093020 + +ID/EX registers + ID/EX.rs = 3, ID/EX.rt = 0 + ID/EX.A = 00000003, ID/EX.B = 00000000 + ID/EX.op = 00 + +EX/MEM registers + EX/MEM.rs = 3, EX/MEM.rt = 0 + EX/MEM.ALUOut = 0000000a, EX/MEM.ALUout = 00000007 + EX/MEM.op = 2b + +MEM/WB registers + MEM/WB.rd = 0, MEM/WB.rt = 3 + MEM/WB.value = ffffffff + EX/MEM.op = 23 + + + +clock cycle = 6 (time = 60) +IF/ID registers + IF/ID.PC+4 = 00000018, IF/ID.IR = ac06000c + +ID/EX registers + ID/EX.rs = 8, ID/EX.rt = 9 + ID/EX.A = 00000008, ID/EX.B = 00000009 + ID/EX.op = 00 + +EX/MEM registers + EX/MEM.rs = 8, EX/MEM.rt = 9 + EX/MEM.ALUOut = ffffffff, EX/MEM.ALUout = 00000000 + EX/MEM.op = 00 + +MEM/WB registers + MEM/WB.rd = 0, MEM/WB.rt = 7 + MEM/WB.value = ffffffff + EX/MEM.op = 2b + + + +clock cycle = 7 (time = 70) +IF/ID registers + IF/ID.PC+4 = 0000001c, IF/ID.IR = 00c05020 + +ID/EX registers + ID/EX.rs = 0, ID/EX.rt = 6 + ID/EX.A = 00000000, ID/EX.B = 00000006 + ID/EX.op = 2b + +EX/MEM registers + EX/MEM.rs = 0, EX/MEM.rt = 6 + EX/MEM.ALUOut = 00000011, EX/MEM.ALUout = 00000009 + EX/MEM.op = 00 + +MEM/WB registers + MEM/WB.rd = 4, MEM/WB.rt = 0 + MEM/WB.value = ffffffff + EX/MEM.op = 00 + + + +clock cycle = 8 (time = 80) +IF/ID registers + IF/ID.PC+4 = 00000020, IF/ID.IR = 8c0b0010 + +ID/EX registers + ID/EX.rs = 6, ID/EX.rt = 0 + ID/EX.A = 00000006, ID/EX.B = 00000000 + ID/EX.op = 00 + +EX/MEM registers + EX/MEM.rs = 6, EX/MEM.rt = 0 + EX/MEM.ALUOut = 0000000c, EX/MEM.ALUout = 00000006 + EX/MEM.op = 2b + +MEM/WB registers + MEM/WB.rd = 6, MEM/WB.rt = 9 + MEM/WB.value = 00000011 + EX/MEM.op = 00 + + + +clock cycle = 9 (time = 90) +IF/ID registers + IF/ID.PC+4 = 00000024, IF/ID.IR = 00000020 + +ID/EX registers + ID/EX.rs = 0, ID/EX.rt = 11 + ID/EX.A = 00000000, ID/EX.B = 0000000b + ID/EX.op = 23 + +EX/MEM registers + EX/MEM.rs = 0, EX/MEM.rt = 11 + EX/MEM.ALUOut = 00000006, EX/MEM.ALUout = 00000000 + EX/MEM.op = 00 + +MEM/WB registers + MEM/WB.rd = 0, MEM/WB.rt = 6 + MEM/WB.value = 00000011 + EX/MEM.op = 2b + + + +clock cycle = 10 (time = 100) +IF/ID registers + IF/ID.PC+4 = 00000028, IF/ID.IR = 002b6020 + +ID/EX registers + ID/EX.rs = 0, ID/EX.rt = 0 + ID/EX.A = 00000000, ID/EX.B = 00000000 + ID/EX.op = 00 + +EX/MEM registers + EX/MEM.rs = 0, EX/MEM.rt = 0 + EX/MEM.ALUOut = 00000010, EX/MEM.ALUout = 0000000b + EX/MEM.op = 23 + +MEM/WB registers + MEM/WB.rd = 10, MEM/WB.rt = 0 + MEM/WB.value = 00000006 + EX/MEM.op = 00 + + + +clock cycle = 11 (time = 110) +IF/ID registers + IF/ID.PC+4 = 0000002c, IF/ID.IR = 00000020 + +ID/EX registers + ID/EX.rs = 1, ID/EX.rt = 11 + ID/EX.A = 00000001, ID/EX.B = 0000000b + ID/EX.op = 00 + +EX/MEM registers + EX/MEM.rs = 1, EX/MEM.rt = 11 + EX/MEM.ALUOut = 00000000, EX/MEM.ALUout = 00000000 + EX/MEM.op = 00 + +MEM/WB registers + MEM/WB.rd = 0, MEM/WB.rt = 11 + MEM/WB.value = fffffffe + EX/MEM.op = 23 + + + +clock cycle = 12 (time = 120) +IF/ID registers + IF/ID.PC+4 = 00000030, IF/ID.IR = 00000020 + +ID/EX registers + ID/EX.rs = 0, ID/EX.rt = 0 + ID/EX.A = 00000000, ID/EX.B = 00000000 + ID/EX.op = 00 + +EX/MEM registers + EX/MEM.rs = 0, EX/MEM.rt = 0 + EX/MEM.ALUOut = 0000000c, EX/MEM.ALUout = 0000000b + EX/MEM.op = 00 + +MEM/WB registers + MEM/WB.rd = 0, MEM/WB.rt = 0 + MEM/WB.value = 00000000 + EX/MEM.op = 00 + + + +clock cycle = 13 (time = 130) +IF/ID registers + IF/ID.PC+4 = 00000034, IF/ID.IR = 00000020 + +ID/EX registers + ID/EX.rs = 0, ID/EX.rt = 0 + ID/EX.A = 00000000, ID/EX.B = 00000000 + ID/EX.op = 00 + +EX/MEM registers + EX/MEM.rs = 0, EX/MEM.rt = 0 + EX/MEM.ALUOut = 00000000, EX/MEM.ALUout = 00000000 + EX/MEM.op = 00 + +MEM/WB registers + MEM/WB.rd = 12, MEM/WB.rt = 11 + MEM/WB.value = 0000000c + EX/MEM.op = 00 + + + +clock cycle = 14 (time = 140) +IF/ID registers + IF/ID.PC+4 = 00000038, IF/ID.IR = 00000020 + +ID/EX registers + ID/EX.rs = 0, ID/EX.rt = 0 + ID/EX.A = 00000000, ID/EX.B = 00000000 + ID/EX.op = 00 + +EX/MEM registers + EX/MEM.rs = 0, EX/MEM.rt = 0 + EX/MEM.ALUOut = 00000000, EX/MEM.ALUout = 00000000 + EX/MEM.op = 00 + +MEM/WB registers + MEM/WB.rd = 0, MEM/WB.rt = 0 + MEM/WB.value = 00000000 + EX/MEM.op = 00 + + + +clock cycle = 15 (time = 150) +IF/ID registers + IF/ID.PC+4 = 0000003c, IF/ID.IR = 00000020 + +ID/EX registers + ID/EX.rs = 0, ID/EX.rt = 0 + ID/EX.A = 00000000, ID/EX.B = 00000000 + ID/EX.op = 00 + +EX/MEM registers + EX/MEM.rs = 0, EX/MEM.rt = 0 + EX/MEM.ALUOut = 00000000, EX/MEM.ALUout = 00000000 + EX/MEM.op = 00 + +MEM/WB registers + MEM/WB.rd = 0, MEM/WB.rt = 0 + MEM/WB.value = 00000000 + EX/MEM.op = 00 + + + +clock cycle = 0 (time = 160) diff --git a/OLD/ee4363/mp2/test_mipspipe.vcd b/OLD/ee4363/mp2/test_mipspipe.vcd new file mode 100644 index 0000000..3e076d6 --- /dev/null +++ b/OLD/ee4363/mp2/test_mipspipe.vcd @@ -0,0 +1,413 @@ +$date + Fri Dec 18 19:19:39 2020 +$end +$version + Icarus Verilog +$end +$timescale + 1s +$end +$scope module test_mipspipe $end +$var reg 1 ! clock $end +$var reg 4 " clock_cycle [3:0] $end +$scope module u_mipspipe_mp2 $end +$var wire 32 # Bin [31:0] $end +$var wire 1 $ STALL $end +$var wire 1 % bypassAfromALUinWB $end +$var wire 1 & bypassAfromLWinWB $end +$var wire 1 ' bypassAfromMEM $end +$var wire 1 ( bypassBfromALUinWB $end +$var wire 1 ) bypassBfromLWinWB $end +$var wire 1 * bypassBfromMEM $end +$var wire 1 + bypassIDEXAfromWB $end +$var wire 1 , bypassIDEXBfromWB $end +$var wire 1 ! clock $end +$var wire 5 - MEMWBrt [4:0] $end +$var wire 5 . MEMWBrd [4:0] $end +$var wire 6 / MEMWBop [5:0] $end +$var wire 5 0 IFIDrt [4:0] $end +$var wire 5 1 IFIDrs [4:0] $end +$var wire 6 2 IFIDop [5:0] $end +$var wire 5 3 IDEXrt [4:0] $end +$var wire 5 4 IDEXrs [4:0] $end +$var wire 6 5 IDEXop [5:0] $end +$var wire 5 6 EXMEMrd [4:0] $end +$var wire 6 7 EXMEMop [5:0] $end +$var wire 32 8 Ain [31:0] $end +$var reg 32 9 EXMEMALUOut [31:0] $end +$var reg 32 : EXMEMB [31:0] $end +$var reg 32 ; EXMEMIR [31:0] $end +$var reg 32 < IDEXA [31:0] $end +$var reg 32 = IDEXB [31:0] $end +$var reg 32 > IDEXIR [31:0] $end +$var reg 32 ? IFIDIR [31:0] $end +$var reg 32 @ MEMWBIR [31:0] $end +$var reg 32 A MEMWBValue [31:0] $end +$var reg 32 B PC [31:0] $end +$var reg 6 C i [5:0] $end +$var reg 11 D j [10:0] $end +$var reg 11 E k [10:0] $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +b10000000000 E +b10000000000 D +b100000 C +b0 B +bx A +b100000 @ +b100000 ? +b100000 > +bx = +bx < +b100000 ; +bx : +bx 9 +bx 8 +b0 7 +b0 6 +b0 5 +b0 4 +b0 3 +b0 2 +b0 1 +b0 0 +b0 / +b0 . +b0 - +1, +1+ +0* +0) +0( +0' +0& +0% +0$ +bx # +b0 " +0! +$end +#5 +0+ +0, +b10 1 +b1 0 +b100 B +b10000010010100000100000 ? +b1 " +1! +#10 +0! +#15 +b10 8 +b10 4 +b1 3 +b1 # +b101 1 +b11 0 +b100011 2 +b10000010010100000100000 > +b1 = +b10 < +b1000 B +b10001100101000110000000000000100 ? +b10 " +1! +#20 +0! +#25 +1' +b11 8 +b101 6 +b101 4 +b11 3 +b100011 5 +b11 # +b111 0 +b101011 2 +b1 : +b10000010010100000100000 ; +b11 9 +b10001100101000110000000000000100 > +b11 = +b101 < +b1100 B +b10101100101001110000000000000101 ? +b11 " +1! +#30 +0! +#35 +0' +b101 . +b1 - +b0 6 +b100011 7 +b101 8 +b111 3 +b101011 5 +b111 # +b11 1 +b0 0 +b0 2 +b10000010010100000100000 @ +b11 A +b11 : +b10001100101000110000000000000100 ; +b111 9 +b10101100101001110000000000000101 > +b111 = +b10000 B +b11000000010000000100000 ? +b100 " +1! +#40 +0! +#45 +1& +b11111111111111111111111111111111 8 +b0 . +b11 - +b100011 / +b101011 7 +b11 4 +b0 3 +b0 5 +b0 # +b1000 1 +b1001 0 +b10001100101000110000000000000100 @ +b11111111111111111111111111111111 A +b111 : +b10101100101001110000000000000101 ; +b1010 9 +b11000000010000000100000 > +b0 = +b11 < +b10100 B +b1000010010011000000100000 ? +b101 " +1! +#50 +0! +#55 +b1000 8 +0& +b111 - +b101011 / +b100 6 +b0 7 +b1000 4 +b1001 3 +b1001 # +b0 1 +b110 0 +b101011 2 +b10101100101001110000000000000101 @ +b0 : +b11000000010000000100000 ; +b11111111111111111111111111111111 9 +b1000010010011000000100000 > +b1001 = +b1000 < +b11000 B +b10101100000001100000000000001100 ? +b110 " +1! +#60 +0! +#65 +b0 8 +b100 . +b0 - +b0 / +b110 6 +b0 4 +b110 3 +b101011 5 +b110 # +b110 1 +b0 0 +b0 2 +b11000000010000000100000 @ +b1001 : +b1000010010011000000100000 ; +b10001 9 +b10101100000001100000000000001100 > +b110 = +b0 < +b11100 B +b110000000101000000100000 ? +b111 " +1! +#70 +0! +#75 +b110 8 +b110 . +b1001 - +b0 6 +b101011 7 +b110 4 +b0 3 +b0 5 +b0 # +b0 1 +b1011 0 +b100011 2 +b1000010010011000000100000 @ +b10001 A +b110 : +b10101100000001100000000000001100 ; +b1100 9 +b110000000101000000100000 > +b0 = +b110 < +b100000 B +b10001100000010110000000000010000 ? +b1000 " +1! +#80 +0! +#85 +0$ +b0 8 +b0 . +b110 - +b101011 / +b1010 6 +b0 7 +b0 4 +b1011 3 +b100011 5 +b1011 # +b0 0 +b0 2 +b10101100000001100000000000001100 @ +b0 : +b110000000101000000100000 ; +b110 9 +b10001100000010110000000000010000 > +b1011 = +b0 < +b100100 B +b100000 ? +b1001 " +1! +#90 +0! +#95 +b1010 . +b0 - +b0 / +b0 6 +b100011 7 +b0 3 +b0 5 +b0 # +b1 1 +b1011 0 +b110000000101000000100000 @ +b110 A +b1011 : +b10001100000010110000000000010000 ; +b10000 9 +b100000 > +b0 = +b101000 B +b1010110110000000100000 ? +b1010 " +1! +#100 +0! +#105 +b1 8 +b0 . +b1011 - +b100011 / +b0 7 +b1 4 +b1011 3 +b1011 # +b0 1 +b0 0 +b10001100000010110000000000010000 @ +b11111111111111111111111111111110 A +b0 : +b100000 ; +b0 9 +b1010110110000000100000 > +b1011 = +b1 < +b101100 B +b100000 ? +b1011 " +1! +#110 +0! +#115 +1+ +1, +b0 8 +b0 - +b0 / +b1100 6 +b0 4 +b0 3 +b0 # +b100000 @ +b0 A +b1011 : +b1010110110000000100000 ; +b1100 9 +b100000 > +b0 = +b0 < +b110000 B +b1100 " +1! +#120 +0! +#125 +0+ +0, +b1100 . +b1011 - +b0 6 +b1010110110000000100000 @ +b1100 A +b0 : +b100000 ; +b0 9 +b110100 B +b1101 " +1! +#130 +0! +#135 +1+ +1, +b0 . +b0 - +b100000 @ +b0 A +b111000 B +b1110 " +1! +#140 +0! +#145 +b111100 B +b1111 " +1! +#150 +0! +#155 +b1000000 B +b0 " +1! +#160 +0! diff --git a/OLD/ee4363/mp2/test_mipspipe_mp2.v b/OLD/ee4363/mp2/test_mipspipe_mp2.v new file mode 100644 index 0000000..f184011 --- /dev/null +++ b/OLD/ee4363/mp2/test_mipspipe_mp2.v @@ -0,0 +1,53 @@ +// +// Test bench for the mipspipe +// Boram Lee +// + +`include "mipspipe_mp2.v" + +module test_mipspipe; + + reg clock; + reg [3:0] clock_cycle; + +// instantiate pipeline module + mipspipe_mp2 u_mipspipe_mp2(clock); + +// initialize clock and cycle counter + initial begin + clock = 0; + clock_cycle=4'h0; + #160 $finish; + end + +// 10 unit clock cycle + always + #5 clock = ~clock; + + always @(posedge clock) + begin + clock_cycle=clock_cycle+1; + end + + +// display contents of pipeline latches at the end of each clock cycle + always @(negedge clock) + begin + $display("\n\nclock cycle = %d",clock_cycle," (time = %1.0t)",$time); + $display("IF/ID registers\n\t IF/ID.PC+4 = %h, IF/ID.IR = %h \n", u_mipspipe_mp2.PC, u_mipspipe_mp2.IFIDIR); + $display("ID/EX registers\n\t ID/EX.rs = %d, ID/EX.rt = %d",u_mipspipe_mp2.IDEXrs,u_mipspipe_mp2.IDEXrt,"\n\t ID/EX.A = %h, ID/EX.B = %h",u_mipspipe_mp2.IDEXA,u_mipspipe_mp2.IDEXB); + $display("\t ID/EX.op = %h\n",u_mipspipe_mp2.IDEXop); + $display("EX/MEM registers\n\t EX/MEM.rs = %d, EX/MEM.rt = %d",u_mipspipe_mp2.IDEXrs,u_mipspipe_mp2.IDEXrt,"\n\t EX/MEM.ALUOut = %h, EX/MEM.ALUout = %h",u_mipspipe_mp2.EXMEMALUOut,u_mipspipe_mp2.EXMEMB); + $display("\t EX/MEM.op = %h\n",u_mipspipe_mp2.EXMEMop); + $display("MEM/WB registers\n\t MEM/WB.rd = %d, MEM/WB.rt = %d",u_mipspipe_mp2.MEMWBrd,u_mipspipe_mp2.MEMWBrt,"\n\t MEM/WB.value = %h",u_mipspipe_mp2.MEMWBValue); + $display("\t EX/MEM.op = %h\n",u_mipspipe_mp2.MEMWBop); + end + +// log to a vcd (variable change dump) file + initial + begin + $dumpfile("test_mipspipe.vcd"); + $dumpvars; + end + +endmodule |