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| author | RossTheRoss <mstrapp@protonmail.com> | 2020-11-21 15:24:04 -0600 |
|---|---|---|
| committer | RossTheRoss <mstrapp@protonmail.com> | 2020-11-21 15:24:04 -0600 |
| commit | 63c9186ad87efb4c28c22296750f6494b2d97e0e (patch) | |
| tree | 8a9b4017b7f90674eb25f784d66161296339dcc3 /ee4363/mp1/MIPSAlu.vcd | |
| parent | add breakout (diff) | |
| download | homework-63c9186ad87efb4c28c22296750f6494b2d97e0e.tar homework-63c9186ad87efb4c28c22296750f6494b2d97e0e.tar.gz homework-63c9186ad87efb4c28c22296750f6494b2d97e0e.tar.bz2 homework-63c9186ad87efb4c28c22296750f6494b2d97e0e.tar.lz homework-63c9186ad87efb4c28c22296750f6494b2d97e0e.tar.xz homework-63c9186ad87efb4c28c22296750f6494b2d97e0e.tar.zst homework-63c9186ad87efb4c28c22296750f6494b2d97e0e.zip | |
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Diffstat (limited to '')
| -rw-r--r-- | ee4363/mp1/MIPSAlu.vcd | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/ee4363/mp1/MIPSAlu.vcd b/ee4363/mp1/MIPSAlu.vcd new file mode 100644 index 0000000..e20e5e6 --- /dev/null +++ b/ee4363/mp1/MIPSAlu.vcd @@ -0,0 +1,57 @@ +$date + Sat Nov 21 15:12:24 2020 +$end +$version + Icarus Verilog +$end +$timescale + 100ps +$end +$scope module test_mipsalu $end +$var wire 1 ! Zero $end +$var wire 32 " ALUOut [31:0] $end +$var reg 32 # A [31:0] $end +$var reg 4 $ ALUctl [3:0] $end +$var reg 32 % B [31:0] $end +$scope module U0 $end +$var wire 32 & A [31:0] $end +$var wire 4 ' ALUctl [3:0] $end +$var wire 32 ( B [31:0] $end +$var wire 1 ! Zero $end +$var reg 32 ) ALUOut [31:0] $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +b0 ) +b1010101010101010101010101010101 ( +bx ' +b1010101010101010101010101010101 & +b1010101010101010101010101010101 % +bx $ +b1010101010101010101010101010101 # +b0 " +1! +$end +#100 +0! +b1010101010101010101010101010101 " +b1010101010101010101010101010101 ) +b0 $ +b0 ' +#200 +b1 $ +b1 ' +#300 +b10101010101010101010101010101010 " +b10101010101010101010101010101010 ) +b10 $ +b10 ' +#400 +1! +b0 " +b0 ) +b110 $ +b110 ' +#500 |