oops

4 files changed, 170 insertions, 166 deletions

diff --git a/ee4363/mp1/MP1_REPORT.pdf b/ee4363/mp1/MP1_REPORT.pdf
new file mode 100644
index 0000000..af00eed
--- /dev/null
+++ b/ee4363/mp1/MP1_REPORT.pdf
diff --git a/ee4363/mp1/MP1_REPORT.pdf:Zone.Identifier b/ee4363/mp1/MP1_REPORT.pdf:Zone.Identifier
new file mode 100644
index 0000000..601cd43
--- /dev/null
+++ b/ee4363/mp1/MP1_REPORT.pdf:Zone.Identifier
@@ -0,0 +1,4 @@
+[ZoneTransfer]

+ZoneId=3

+ReferrerUrl=https://docs.google.com/

+HostUrl=https://doc-14-4o-docstext.googleusercontent.com/export/2khfkjf277mb9qvjh5vf2djetk/70g4nk0ub823mtptvc2o48e6bg/1607046410000/115027284957771899107/115027284957771899107/1Y39LExLlP9z7qI90V5v7FwhH1LFUKaoGjkk3XzQX_NA?format=pdf&id=1Y39LExLlP9z7qI90V5v7FwhH1LFUKaoGjkk3XzQX_NA&token=AC4w5Vji-LXbhP1dDeKZeq1B2plD1aaGqw:1607046179250&ouid=115027284957771899107&includes_info_params=true&inspectorResult=%7B%22pc%22:12,%22lplc%22:5%7D&dat=AJ7Y-hSZ2_M6PdIczdMIOlL8dcAzSdaHKvkcZkLrudIWmoasFTb30LQrAo-Z5sDIO4n5vejco9sMQ-JwYFh9odGLQE-okg8-P8-i_qtKbIWUqD1Y_ophdLNkAgaj-pGtq6fHNBOLGC4h5ATE98NlP1q5_Woo7EgPg1tgfoK6ydNgk_ctW8KQlDSAQjqTZVvJT0oPQtZJkcjzV3JLAt0UO2SzDsKybMBnWdi83d6auSwQLxwoiJ3iXG2FkyDMKLj1ILmLhUNUBiXmaamRX_Xa-PUa1z-_-6j-lvkYcRfcWmDmsbyaSj7D5UqEykNFicgH5iIqiOV68L2SkN8YxV5ZBojsrOk7u3tok1vVlshJ795yEx_BiVCL53-1dU_031oMMrw8tWwsPd2_WiI4-h4Yd9cGjyLm1yZLuX2nuyxCsVhh39cCQ4aeNkbSjIxCUsB5uAN3huYn6G1-g9IoHIUHXgIsHoa4T34tnhMK_q5Kc2V8l6d8tsW7bm3apjhC3_ztluJ7oAiDD_TzbHqSLFXW1l7wZf_sGvI0s3AgTVJNpVySO7a60afBH6PwiTC-3JhGcOnImR1-GXdbjHLbgKXeBp1hg3114eTd1OGToyfb5yDYCDulDOyiXI9iVgCVQzY0XWCubpeWL2rHYh_9-cba9HqCaOZs5iueTKwq

diff --git a/ee4363/mp1/mp12/out b/ee4363/mp1/mp12/out
index 5a975c9..9bb25bb 100644
--- a/ee4363/mp1/mp12/out
+++ b/ee4363/mp1/mp12/out
@@ -6,239 +6,239 @@
 :vpi_module "vhdl_sys";
 :vpi_module "v2005_math";
 :vpi_module "va_math";
-S_0x55c7b7006e40 .scope module, "test_mipspipe" "test_mipspipe" 2 8;
+S_0x55b4011cce40 .scope module, "test_mipspipe" "test_mipspipe" 2 8;
  .timescale 0 0;
-v0x55c7b704a350_0 .var "clock", 0 0;
-v0x55c7b704a3f0_0 .var "clock_cycle", 3 0;
-E_0x55c7b701af80 .event negedge, v0x55c7b7049fb0_0;
-S_0x55c7b70069a0 .scope module, "u_mipspipe" "mipspipe" 2 14, 3 3 0, S_0x55c7b7006e40;
+v0x55b401210350_0 .var "clock", 0 0;
+v0x55b4012103f0_0 .var "clock_cycle", 3 0;
+E_0x55b4011e0f80 .event negedge, v0x55b40120ffb0_0;
+S_0x55b4011cc9a0 .scope module, "u_mipspipe" "mipspipe" 2 14, 3 3 0, S_0x55b4011cce40;
  .timescale 0 0;
     .port_info 0 /INPUT 1 "clock"
-P_0x55c7b70072e0 .param/l "ALUop" 0 3 8, C4<000000>;
-P_0x55c7b7007320 .param/l "BEQ" 0 3 8, C4<000100>;
-P_0x55c7b7007360 .param/l "LW" 0 3 8, C4<100011>;
-P_0x55c7b70073a0 .param/l "SW" 0 3 8, C4<101011>;
-P_0x55c7b70073e0 .param/l "nop" 0 3 8, C4<00000000000000000000000000100000>;
-L_0x55c7b6fe1a40 .functor BUFZ 32, v0x55c7b70492d0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
-L_0x55c7b6fe1820 .functor BUFZ 32, v0x55c7b70493b0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
-v0x55c7b7010de0_0 .net "Ain", 31 0, L_0x55c7b6fe1a40;  1 drivers
-v0x55c7b7048ca0_0 .net "Bin", 31 0, L_0x55c7b6fe1820;  1 drivers
-v0x55c7b7048d80 .array "DMemory", 1023 0, 31 0;
-v0x55c7b7048e20_0 .var "EXMEMALUOut", 31 0;
-v0x55c7b7048f00_0 .var "EXMEMB", 31 0;
-v0x55c7b7049030_0 .var "EXMEMIR", 31 0;
-v0x55c7b7049110_0 .net "EXMEMop", 5 0, L_0x55c7b704a910;  1 drivers
-v0x55c7b70491f0_0 .net "EXMEMrd", 4 0, L_0x55c7b704a5f0;  1 drivers
-v0x55c7b70492d0_0 .var "IDEXA", 31 0;
-v0x55c7b70493b0_0 .var "IDEXB", 31 0;
-v0x55c7b7049490_0 .var "IDEXIR", 31 0;
-v0x55c7b7049570_0 .net "IDEXop", 5 0, L_0x55c7b704aae0;  1 drivers
-v0x55c7b7049650_0 .net "IDEXrs", 4 0, L_0x55c7b704a4b0;  1 drivers
-v0x55c7b7049730_0 .net "IDEXrt", 4 0, L_0x55c7b704a550;  1 drivers
-v0x55c7b7049810_0 .var "IFIDIR", 31 0;
-v0x55c7b70498f0 .array "IMemory", 1023 0, 31 0;
-v0x55c7b70499b0_0 .var "MEMWBIR", 31 0;
-v0x55c7b7049a90_0 .var "MEMWBValue", 31 0;
-v0x55c7b7049b70_0 .net "MEMWBop", 5 0, L_0x55c7b704aa40;  1 drivers
-v0x55c7b7049c50_0 .net "MEMWBrd", 4 0, L_0x55c7b704a6c0;  1 drivers
-v0x55c7b7049d30_0 .net "MEMWBrt", 4 0, L_0x55c7b704a7f0;  1 drivers
-v0x55c7b7049e10_0 .var "PC", 31 0;
-v0x55c7b7049ef0 .array "Regs", 31 0, 31 0;
-v0x55c7b7049fb0_0 .net "clock", 0 0, v0x55c7b704a350_0;  1 drivers
-v0x55c7b704a070_0 .var "i", 5 0;
-v0x55c7b704a150_0 .var "j", 10 0;
-v0x55c7b704a230_0 .var "k", 10 0;
-E_0x55c7b701b270 .event posedge, v0x55c7b7049fb0_0;
-L_0x55c7b704a4b0 .part v0x55c7b7049490_0, 21, 5;
-L_0x55c7b704a550 .part v0x55c7b7049490_0, 16, 5;
-L_0x55c7b704a5f0 .part v0x55c7b7049030_0, 11, 5;
-L_0x55c7b704a6c0 .part v0x55c7b70499b0_0, 11, 5;
-L_0x55c7b704a7f0 .part v0x55c7b70499b0_0, 16, 5;
-L_0x55c7b704a910 .part v0x55c7b7049030_0, 26, 6;
-L_0x55c7b704aa40 .part v0x55c7b70499b0_0, 26, 6;
-L_0x55c7b704aae0 .part v0x55c7b7049490_0, 26, 6;
-    .scope S_0x55c7b70069a0;
+P_0x55b4011cd2e0 .param/l "ALUop" 0 3 8, C4<000000>;
+P_0x55b4011cd320 .param/l "BEQ" 0 3 8, C4<000100>;
+P_0x55b4011cd360 .param/l "LW" 0 3 8, C4<100011>;
+P_0x55b4011cd3a0 .param/l "SW" 0 3 8, C4<101011>;
+P_0x55b4011cd3e0 .param/l "nop" 0 3 8, C4<00000000000000000000000000100000>;
+L_0x55b4011a7a40 .functor BUFZ 32, v0x55b40120f2d0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+L_0x55b4011a7820 .functor BUFZ 32, v0x55b40120f3b0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+v0x55b4011d6de0_0 .net "Ain", 31 0, L_0x55b4011a7a40;  1 drivers
+v0x55b40120eca0_0 .net "Bin", 31 0, L_0x55b4011a7820;  1 drivers
+v0x55b40120ed80 .array "DMemory", 1023 0, 31 0;
+v0x55b40120ee20_0 .var "EXMEMALUOut", 31 0;
+v0x55b40120ef00_0 .var "EXMEMB", 31 0;
+v0x55b40120f030_0 .var "EXMEMIR", 31 0;
+v0x55b40120f110_0 .net "EXMEMop", 5 0, L_0x55b401210910;  1 drivers
+v0x55b40120f1f0_0 .net "EXMEMrd", 4 0, L_0x55b4012105f0;  1 drivers
+v0x55b40120f2d0_0 .var "IDEXA", 31 0;
+v0x55b40120f3b0_0 .var "IDEXB", 31 0;
+v0x55b40120f490_0 .var "IDEXIR", 31 0;
+v0x55b40120f570_0 .net "IDEXop", 5 0, L_0x55b401210ae0;  1 drivers
+v0x55b40120f650_0 .net "IDEXrs", 4 0, L_0x55b4012104b0;  1 drivers
+v0x55b40120f730_0 .net "IDEXrt", 4 0, L_0x55b401210550;  1 drivers
+v0x55b40120f810_0 .var "IFIDIR", 31 0;
+v0x55b40120f8f0 .array "IMemory", 1023 0, 31 0;
+v0x55b40120f9b0_0 .var "MEMWBIR", 31 0;
+v0x55b40120fa90_0 .var "MEMWBValue", 31 0;
+v0x55b40120fb70_0 .net "MEMWBop", 5 0, L_0x55b401210a40;  1 drivers
+v0x55b40120fc50_0 .net "MEMWBrd", 4 0, L_0x55b4012106c0;  1 drivers
+v0x55b40120fd30_0 .net "MEMWBrt", 4 0, L_0x55b4012107f0;  1 drivers
+v0x55b40120fe10_0 .var "PC", 31 0;
+v0x55b40120fef0 .array "Regs", 31 0, 31 0;
+v0x55b40120ffb0_0 .net "clock", 0 0, v0x55b401210350_0;  1 drivers
+v0x55b401210070_0 .var "i", 5 0;
+v0x55b401210150_0 .var "j", 10 0;
+v0x55b401210230_0 .var "k", 10 0;
+E_0x55b4011e1270 .event posedge, v0x55b40120ffb0_0;
+L_0x55b4012104b0 .part v0x55b40120f490_0, 21, 5;
+L_0x55b401210550 .part v0x55b40120f490_0, 16, 5;
+L_0x55b4012105f0 .part v0x55b40120f030_0, 11, 5;
+L_0x55b4012106c0 .part v0x55b40120f9b0_0, 11, 5;
+L_0x55b4012107f0 .part v0x55b40120f9b0_0, 16, 5;
+L_0x55b401210910 .part v0x55b40120f030_0, 26, 6;
+L_0x55b401210a40 .part v0x55b40120f9b0_0, 26, 6;
+L_0x55b401210ae0 .part v0x55b40120f490_0, 26, 6;
+    .scope S_0x55b4011cc9a0;
 T_0 ;
     %pushi/vec4 0, 0, 32;
-    %store/vec4 v0x55c7b7049e10_0, 0, 32;
+    %store/vec4 v0x55b40120fe10_0, 0, 32;
     %pushi/vec4 32, 0, 32;
-    %store/vec4 v0x55c7b7049810_0, 0, 32;
+    %store/vec4 v0x55b40120f810_0, 0, 32;
     %pushi/vec4 32, 0, 32;
-    %store/vec4 v0x55c7b7049490_0, 0, 32;
+    %store/vec4 v0x55b40120f490_0, 0, 32;
     %pushi/vec4 32, 0, 32;
-    %store/vec4 v0x55c7b7049030_0, 0, 32;
+    %store/vec4 v0x55b40120f030_0, 0, 32;
     %pushi/vec4 32, 0, 32;
-    %store/vec4 v0x55c7b70499b0_0, 0, 32;
+    %store/vec4 v0x55b40120f9b0_0, 0, 32;
     %pushi/vec4 0, 0, 6;
-    %store/vec4 v0x55c7b704a070_0, 0, 6;
+    %store/vec4 v0x55b401210070_0, 0, 6;
 T_0.0 ;
-    %load/vec4 v0x55c7b704a070_0;
+    %load/vec4 v0x55b401210070_0;
     %pad/u 32;
     %cmpi/u 31, 0, 32;
     %flag_or 5, 4;
     %jmp/0xz T_0.1, 5;
-    %load/vec4 v0x55c7b704a070_0;
+    %load/vec4 v0x55b401210070_0;
     %pad/u 32;
-    %load/vec4 v0x55c7b704a070_0;
+    %load/vec4 v0x55b401210070_0;
     %pad/u 7;
     %ix/vec4 4;
-    %store/vec4a v0x55c7b7049ef0, 4, 0;
-    %load/vec4 v0x55c7b704a070_0;
+    %store/vec4a v0x55b40120fef0, 4, 0;
+    %load/vec4 v0x55b401210070_0;
     %addi 1, 0, 6;
-    %store/vec4 v0x55c7b704a070_0, 0, 6;
+    %store/vec4 v0x55b401210070_0, 0, 6;
     %jmp T_0.0;
 T_0.1 ;
     %pushi/vec4 4270112, 0, 32;
     %ix/load 4, 0, 0;
     %flag_set/imm 4, 0;
-    %store/vec4a v0x55c7b70498f0, 4, 0;
+    %store/vec4a v0x55b40120f8f0, 4, 0;
     %pushi/vec4 32, 0, 32;
     %ix/load 4, 1, 0;
     %flag_set/imm 4, 0;
-    %store/vec4a v0x55c7b70498f0, 4, 0;
+    %store/vec4a v0x55b40120f8f0, 4, 0;
     %pushi/vec4 32, 0, 32;
     %ix/load 4, 2, 0;
     %flag_set/imm 4, 0;
-    %store/vec4a v0x55c7b70498f0, 4, 0;
+    %store/vec4a v0x55b40120f8f0, 4, 0;
     %pushi/vec4 32, 0, 32;
     %ix/load 4, 3, 0;
     %flag_set/imm 4, 0;
-    %store/vec4a v0x55c7b70498f0, 4, 0;
+    %store/vec4a v0x55b40120f8f0, 4, 0;
     %pushi/vec4 2359492612, 0, 32;
     %ix/load 4, 4, 0;
     %flag_set/imm 4, 0;
-    %store/vec4a v0x55c7b70498f0, 4, 0;
+    %store/vec4a v0x55b40120f8f0, 4, 0;
     %pushi/vec4 2353135616, 0, 32;
     %ix/load 4, 5, 0;
     %flag_set/imm 4, 0;
-    %store/vec4a v0x55c7b70498f0, 4, 0;
+    %store/vec4a v0x55b40120f8f0, 4, 0;
     %pushi/vec4 32, 0, 32;
     %ix/load 4, 6, 0;
     %flag_set/imm 4, 0;
-    %store/vec4a v0x55c7b70498f0, 4, 0;
+    %store/vec4a v0x55b40120f8f0, 4, 0;
     %pushi/vec4 32, 0, 32;
     %ix/load 4, 7, 0;
     %flag_set/imm 4, 0;
-    %store/vec4a v0x55c7b70498f0, 4, 0;
+    %store/vec4a v0x55b40120f8f0, 4, 0;
     %pushi/vec4 10688549, 0, 32;
     %ix/load 4, 8, 0;
     %flag_set/imm 4, 0;
-    %store/vec4a v0x55c7b70498f0, 4, 0;
+    %store/vec4a v0x55b40120f8f0, 4, 0;
     %pushi/vec4 32, 0, 32;
     %ix/load 4, 9, 0;
     %flag_set/imm 4, 0;
-    %store/vec4a v0x55c7b70498f0, 4, 0;
+    %store/vec4a v0x55b40120f8f0, 4, 0;
     %pushi/vec4 32, 0, 32;
     %ix/load 4, 10, 0;
     %flag_set/imm 4, 0;
-    %store/vec4a v0x55c7b70498f0, 4, 0;
+    %store/vec4a v0x55b40120f8f0, 4, 0;
     %pushi/vec4 32, 0, 32;
     %ix/load 4, 11, 0;
     %flag_set/imm 4, 0;
-    %store/vec4a v0x55c7b70498f0, 4, 0;
+    %store/vec4a v0x55b40120f8f0, 4, 0;
     %pushi/vec4 2896363520, 0, 32;
     %ix/load 4, 12, 0;
     %flag_set/imm 4, 0;
-    %store/vec4a v0x55c7b70498f0, 4, 0;
+    %store/vec4a v0x55b40120f8f0, 4, 0;
     %pushi/vec4 13, 0, 11;
-    %store/vec4 v0x55c7b704a150_0, 0, 11;
+    %store/vec4 v0x55b401210150_0, 0, 11;
 T_0.2 ;
-    %load/vec4 v0x55c7b704a150_0;
+    %load/vec4 v0x55b401210150_0;
     %pad/u 32;
     %cmpi/u 1023, 0, 32;
     %flag_or 5, 4;
     %jmp/0xz T_0.3, 5;
     %pushi/vec4 32, 0, 32;
-    %load/vec4 v0x55c7b704a150_0;
+    %load/vec4 v0x55b401210150_0;
     %pad/u 12;
     %ix/vec4 4;
-    %store/vec4a v0x55c7b70498f0, 4, 0;
-    %load/vec4 v0x55c7b704a150_0;
+    %store/vec4a v0x55b40120f8f0, 4, 0;
+    %load/vec4 v0x55b401210150_0;
     %addi 1, 0, 11;
-    %store/vec4 v0x55c7b704a150_0, 0, 11;
+    %store/vec4 v0x55b401210150_0, 0, 11;
     %jmp T_0.2;
 T_0.3 ;
     %pushi/vec4 0, 0, 32;
     %ix/load 4, 0, 0;
     %flag_set/imm 4, 0;
-    %store/vec4a v0x55c7b7048d80, 4, 0;
+    %store/vec4a v0x55b40120ed80, 4, 0;
     %pushi/vec4 4294967295, 0, 32;
     %ix/load 4, 1, 0;
     %flag_set/imm 4, 0;
-    %store/vec4a v0x55c7b7048d80, 4, 0;
+    %store/vec4a v0x55b40120ed80, 4, 0;
     %pushi/vec4 2, 0, 11;
-    %store/vec4 v0x55c7b704a230_0, 0, 11;
+    %store/vec4 v0x55b401210230_0, 0, 11;
 T_0.4 ;
-    %load/vec4 v0x55c7b704a230_0;
+    %load/vec4 v0x55b401210230_0;
     %pad/u 32;
     %cmpi/u 1023, 0, 32;
     %flag_or 5, 4;
     %jmp/0xz T_0.5, 5;
     %pushi/vec4 0, 0, 32;
-    %load/vec4 v0x55c7b704a230_0;
+    %load/vec4 v0x55b401210230_0;
     %pad/u 12;
     %ix/vec4 4;
-    %store/vec4a v0x55c7b7048d80, 4, 0;
-    %load/vec4 v0x55c7b704a230_0;
+    %store/vec4a v0x55b40120ed80, 4, 0;
+    %load/vec4 v0x55b401210230_0;
     %addi 1, 0, 11;
-    %store/vec4 v0x55c7b704a230_0, 0, 11;
+    %store/vec4 v0x55b401210230_0, 0, 11;
     %jmp T_0.4;
 T_0.5 ;
     %end;
     .thread T_0;
-    .scope S_0x55c7b70069a0;
+    .scope S_0x55b4011cc9a0;
 T_1 ;
-    %wait E_0x55c7b701b270;
-    %load/vec4 v0x55c7b7049e10_0;
+    %wait E_0x55b4011e1270;
+    %load/vec4 v0x55b40120fe10_0;
     %ix/load 5, 2, 0;
     %flag_set/imm 4, 0;
     %shiftr 5;
     %ix/vec4 4;
-    %load/vec4a v0x55c7b70498f0, 4;
-    %assign/vec4 v0x55c7b7049810_0, 0;
-    %load/vec4 v0x55c7b7049e10_0;
+    %load/vec4a v0x55b40120f8f0, 4;
+    %assign/vec4 v0x55b40120f810_0, 0;
+    %load/vec4 v0x55b40120fe10_0;
     %addi 4, 0, 32;
-    %assign/vec4 v0x55c7b7049e10_0, 0;
-    %load/vec4 v0x55c7b7049810_0;
+    %assign/vec4 v0x55b40120fe10_0, 0;
+    %load/vec4 v0x55b40120f810_0;
     %parti/s 5, 21, 6;
     %pad/u 7;
     %ix/vec4 4;
-    %load/vec4a v0x55c7b7049ef0, 4;
-    %assign/vec4 v0x55c7b70492d0_0, 0;
-    %load/vec4 v0x55c7b7049810_0;
+    %load/vec4a v0x55b40120fef0, 4;
+    %assign/vec4 v0x55b40120f2d0_0, 0;
+    %load/vec4 v0x55b40120f810_0;
     %parti/s 5, 16, 6;
     %pad/u 7;
     %ix/vec4 4;
-    %load/vec4a v0x55c7b7049ef0, 4;
-    %assign/vec4 v0x55c7b70493b0_0, 0;
-    %load/vec4 v0x55c7b7049810_0;
-    %assign/vec4 v0x55c7b7049490_0, 0;
-    %load/vec4 v0x55c7b7049570_0;
+    %load/vec4a v0x55b40120fef0, 4;
+    %assign/vec4 v0x55b40120f3b0_0, 0;
+    %load/vec4 v0x55b40120f810_0;
+    %assign/vec4 v0x55b40120f490_0, 0;
+    %load/vec4 v0x55b40120f570_0;
     %pushi/vec4 35, 0, 6;
     %cmp/e;
     %flag_get/vec4 4;
-    %load/vec4 v0x55c7b7049570_0;
+    %load/vec4 v0x55b40120f570_0;
     %pushi/vec4 43, 0, 6;
     %cmp/e;
     %flag_get/vec4 4;
     %or;
     %flag_set/vec4 8;
     %jmp/0xz  T_1.0, 8;
-    %load/vec4 v0x55c7b70492d0_0;
-    %load/vec4 v0x55c7b7049490_0;
+    %load/vec4 v0x55b40120f2d0_0;
+    %load/vec4 v0x55b40120f490_0;
     %parti/s 1, 15, 5;
     %replicate 16;
-    %load/vec4 v0x55c7b7049490_0;
+    %load/vec4 v0x55b40120f490_0;
     %parti/s 16, 0, 2;
     %concat/vec4; draw_concat_vec4
     %add;
-    %assign/vec4 v0x55c7b7048e20_0, 0;
+    %assign/vec4 v0x55b40120ee20_0, 0;
     %jmp T_1.1;
 T_1.0 ;
-    %load/vec4 v0x55c7b7049570_0;
+    %load/vec4 v0x55b40120f570_0;
     %cmpi/e 0, 0, 6;
     %jmp/0xz  T_1.2, 4;
-    %load/vec4 v0x55c7b7049490_0;
+    %load/vec4 v0x55b40120f490_0;
     %parti/s 6, 0, 2;
     %dup/vec4;
     %pushi/vec4 32, 0, 6;
@@ -250,65 +250,65 @@ T_1.0 ;
     %jmp/1 T_1.5, 6;
     %jmp T_1.7;
 T_1.4 ;
-    %load/vec4 v0x55c7b7010de0_0;
-    %load/vec4 v0x55c7b7048ca0_0;
+    %load/vec4 v0x55b4011d6de0_0;
+    %load/vec4 v0x55b40120eca0_0;
     %add;
-    %assign/vec4 v0x55c7b7048e20_0, 0;
+    %assign/vec4 v0x55b40120ee20_0, 0;
     %jmp T_1.7;
 T_1.5 ;
-    %load/vec4 v0x55c7b7010de0_0;
-    %load/vec4 v0x55c7b7048ca0_0;
+    %load/vec4 v0x55b4011d6de0_0;
+    %load/vec4 v0x55b40120eca0_0;
     %or;
-    %assign/vec4 v0x55c7b7048e20_0, 0;
+    %assign/vec4 v0x55b40120ee20_0, 0;
     %jmp T_1.7;
 T_1.7 ;
     %pop/vec4 1;
 T_1.2 ;
 T_1.1 ;
-    %load/vec4 v0x55c7b7049490_0;
-    %assign/vec4 v0x55c7b7049030_0, 0;
-    %load/vec4 v0x55c7b70493b0_0;
-    %assign/vec4 v0x55c7b7048f00_0, 0;
-    %load/vec4 v0x55c7b7049110_0;
+    %load/vec4 v0x55b40120f490_0;
+    %assign/vec4 v0x55b40120f030_0, 0;
+    %load/vec4 v0x55b40120f3b0_0;
+    %assign/vec4 v0x55b40120ef00_0, 0;
+    %load/vec4 v0x55b40120f110_0;
     %cmpi/e 0, 0, 6;
     %jmp/0xz  T_1.8, 4;
-    %load/vec4 v0x55c7b7048e20_0;
-    %assign/vec4 v0x55c7b7049a90_0, 0;
+    %load/vec4 v0x55b40120ee20_0;
+    %assign/vec4 v0x55b40120fa90_0, 0;
     %jmp T_1.9;
 T_1.8 ;
-    %load/vec4 v0x55c7b7049110_0;
+    %load/vec4 v0x55b40120f110_0;
     %cmpi/e 35, 0, 6;
     %jmp/0xz  T_1.10, 4;
-    %load/vec4 v0x55c7b7048e20_0;
+    %load/vec4 v0x55b40120ee20_0;
     %ix/load 5, 2, 0;
     %flag_set/imm 4, 0;
     %shiftr 5;
     %ix/vec4 4;
-    %load/vec4a v0x55c7b7048d80, 4;
-    %assign/vec4 v0x55c7b7049a90_0, 0;
+    %load/vec4a v0x55b40120ed80, 4;
+    %assign/vec4 v0x55b40120fa90_0, 0;
     %jmp T_1.11;
 T_1.10 ;
-    %load/vec4 v0x55c7b7049110_0;
+    %load/vec4 v0x55b40120f110_0;
     %cmpi/e 43, 0, 6;
     %jmp/0xz  T_1.12, 4;
-    %load/vec4 v0x55c7b7048f00_0;
-    %load/vec4 v0x55c7b7048e20_0;
+    %load/vec4 v0x55b40120ef00_0;
+    %load/vec4 v0x55b40120ee20_0;
     %ix/load 4, 2, 0;
     %flag_set/imm 4, 0;
     %shiftr 4;
     %ix/vec4 3;
     %ix/load 4, 0, 0; Constant delay
-    %assign/vec4/a/d v0x55c7b7048d80, 0, 4;
+    %assign/vec4/a/d v0x55b40120ed80, 0, 4;
 T_1.12 ;
 T_1.11 ;
 T_1.9 ;
-    %load/vec4 v0x55c7b7049030_0;
-    %assign/vec4 v0x55c7b70499b0_0, 0;
-    %load/vec4 v0x55c7b7049b70_0;
+    %load/vec4 v0x55b40120f030_0;
+    %assign/vec4 v0x55b40120f9b0_0, 0;
+    %load/vec4 v0x55b40120fb70_0;
     %pushi/vec4 0, 0, 6;
     %cmp/e;
     %flag_get/vec4 4;
-    %load/vec4 v0x55c7b7049c50_0;
+    %load/vec4 v0x55b40120fc50_0;
     %pad/u 32;
     %pushi/vec4 0, 0, 32;
     %cmp/e;
@@ -317,19 +317,19 @@ T_1.9 ;
     %and;
     %flag_set/vec4 8;
     %jmp/0xz  T_1.14, 8;
-    %load/vec4 v0x55c7b7049a90_0;
-    %load/vec4 v0x55c7b7049c50_0;
+    %load/vec4 v0x55b40120fa90_0;
+    %load/vec4 v0x55b40120fc50_0;
     %pad/u 7;
     %ix/vec4 3;
     %ix/load 4, 0, 0; Constant delay
-    %assign/vec4/a/d v0x55c7b7049ef0, 0, 4;
+    %assign/vec4/a/d v0x55b40120fef0, 0, 4;
     %jmp T_1.15;
 T_1.14 ;
-    %load/vec4 v0x55c7b7049b70_0;
+    %load/vec4 v0x55b40120fb70_0;
     %pushi/vec4 35, 0, 6;
     %cmp/e;
     %flag_get/vec4 4;
-    %load/vec4 v0x55c7b7049d30_0;
+    %load/vec4 v0x55b40120fd30_0;
     %pad/u 32;
     %pushi/vec4 0, 0, 32;
     %cmp/e;
@@ -338,56 +338,56 @@ T_1.14 ;
     %and;
     %flag_set/vec4 8;
     %jmp/0xz  T_1.16, 8;
-    %load/vec4 v0x55c7b7049a90_0;
-    %load/vec4 v0x55c7b7049d30_0;
+    %load/vec4 v0x55b40120fa90_0;
+    %load/vec4 v0x55b40120fd30_0;
     %pad/u 7;
     %ix/vec4 3;
     %ix/load 4, 0, 0; Constant delay
-    %assign/vec4/a/d v0x55c7b7049ef0, 0, 4;
+    %assign/vec4/a/d v0x55b40120fef0, 0, 4;
 T_1.16 ;
 T_1.15 ;
     %jmp T_1;
     .thread T_1;
-    .scope S_0x55c7b7006e40;
+    .scope S_0x55b4011cce40;
 T_2 ;
     %pushi/vec4 0, 0, 1;
-    %store/vec4 v0x55c7b704a350_0, 0, 1;
+    %store/vec4 v0x55b401210350_0, 0, 1;
     %pushi/vec4 0, 0, 4;
-    %store/vec4 v0x55c7b704a3f0_0, 0, 4;
+    %store/vec4 v0x55b4012103f0_0, 0, 4;
     %delay 160, 0;
     %vpi_call 2 20 "$finish" {0 0 0};
     %end;
     .thread T_2;
-    .scope S_0x55c7b7006e40;
+    .scope S_0x55b4011cce40;
 T_3 ;
     %delay 5, 0;
-    %load/vec4 v0x55c7b704a350_0;
+    %load/vec4 v0x55b401210350_0;
     %inv;
-    %store/vec4 v0x55c7b704a350_0, 0, 1;
+    %store/vec4 v0x55b401210350_0, 0, 1;
     %jmp T_3;
     .thread T_3;
-    .scope S_0x55c7b7006e40;
+    .scope S_0x55b4011cce40;
 T_4 ;
-    %wait E_0x55c7b701b270;
-    %load/vec4 v0x55c7b704a3f0_0;
+    %wait E_0x55b4011e1270;
+    %load/vec4 v0x55b4012103f0_0;
     %addi 1, 0, 4;
-    %store/vec4 v0x55c7b704a3f0_0, 0, 4;
+    %store/vec4 v0x55b4012103f0_0, 0, 4;
     %jmp T_4;
     .thread T_4;
-    .scope S_0x55c7b7006e40;
+    .scope S_0x55b4011cce40;
 T_5 ;
-    %wait E_0x55c7b701af80;
-    %vpi_call 2 36 "$display", "\012\012clock cycle = %d", v0x55c7b704a3f0_0, " (time = %1.0t)", $time {0 0 0};
-    %vpi_call 2 37 "$display", "IF/ID registers\012\011 IF/ID.PC+4 = %h, IF/ID.IR = %h \012", v0x55c7b7049e10_0, v0x55c7b7049810_0 {0 0 0};
-    %vpi_call 2 38 "$display", "ID/EX registers\012\011 ID/EX.rs = %d, ID/EX.rt = %d", v0x55c7b7049650_0, v0x55c7b7049730_0, "\012\011 ID/EX.A = %h, ID/EX.B = %h", v0x55c7b70492d0_0, v0x55c7b70493b0_0 {0 0 0};
-    %vpi_call 2 39 "$display", "\011 ID/EX.op = %h\012", v0x55c7b7049570_0 {0 0 0};
-    %vpi_call 2 40 "$display", "EX/MEM registers\012\011 EX/MEM.rs = %d, EX/MEM.rt = %d", v0x55c7b7049650_0, v0x55c7b7049730_0, "\012\011 EX/MEM.ALUOut = %h, EX/MEM.ALUout = %h", v0x55c7b7048e20_0, v0x55c7b7048f00_0 {0 0 0};
-    %vpi_call 2 41 "$display", "\011 EX/MEM.op = %h\012", v0x55c7b7049110_0 {0 0 0};
-    %vpi_call 2 42 "$display", "MEM/WB registers\012\011 MEM/WB.rd = %d, MEM/WB.rt = %d", v0x55c7b7049c50_0, v0x55c7b7049d30_0, "\012\011 MEM/WB.value = %h", v0x55c7b7049a90_0 {0 0 0};
-    %vpi_call 2 43 "$display", "\011 EX/MEM.op = %h\012", v0x55c7b7049b70_0 {0 0 0};
+    %wait E_0x55b4011e0f80;
+    %vpi_call 2 36 "$display", "\012\012clock cycle = %d", v0x55b4012103f0_0, " (time = %1.0t)", $time {0 0 0};
+    %vpi_call 2 37 "$display", "IF/ID registers\012\011 IF/ID.PC+4 = %h, IF/ID.IR = %h \012", v0x55b40120fe10_0, v0x55b40120f810_0 {0 0 0};
+    %vpi_call 2 38 "$display", "ID/EX registers\012\011 ID/EX.rs = %d, ID/EX.rt = %d", v0x55b40120f650_0, v0x55b40120f730_0, "\012\011 ID/EX.A = %h, ID/EX.B = %h", v0x55b40120f2d0_0, v0x55b40120f3b0_0 {0 0 0};
+    %vpi_call 2 39 "$display", "\011 ID/EX.op = %h\012", v0x55b40120f570_0 {0 0 0};
+    %vpi_call 2 40 "$display", "EX/MEM registers\012\011 EX/MEM.rs = %d, EX/MEM.rt = %d", v0x55b40120f650_0, v0x55b40120f730_0, "\012\011 EX/MEM.ALUOut = %h, EX/MEM.ALUout = %h", v0x55b40120ee20_0, v0x55b40120ef00_0 {0 0 0};
+    %vpi_call 2 41 "$display", "\011 EX/MEM.op = %h\012", v0x55b40120f110_0 {0 0 0};
+    %vpi_call 2 42 "$display", "MEM/WB registers\012\011 MEM/WB.rd = %d, MEM/WB.rt = %d", v0x55b40120fc50_0, v0x55b40120fd30_0, "\012\011 MEM/WB.value = %h", v0x55b40120fa90_0 {0 0 0};
+    %vpi_call 2 43 "$display", "\011 EX/MEM.op = %h\012", v0x55b40120fb70_0 {0 0 0};
     %jmp T_5;
     .thread T_5;
-    .scope S_0x55c7b7006e40;
+    .scope S_0x55b4011cce40;
 T_6 ;
     %vpi_call 2 49 "$dumpfile", "test_mipspipe.vcd" {0 0 0};
     %vpi_call 2 50 "$dumpvars" {0 0 0};
diff --git a/ee4363/mp1/mp12/test_mipspipe.vcd b/ee4363/mp1/mp12/test_mipspipe.vcd
index 9a6b26f..d70b8fd 100644
--- a/ee4363/mp1/mp12/test_mipspipe.vcd
+++ b/ee4363/mp1/mp12/test_mipspipe.vcd
@@ -1,5 +1,5 @@
 $date
-	Thu Dec  3 12:05:26 2020
+	Thu Dec  3 19:41:59 2020
 $end
 $version
 	Icarus Verilog