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-rw-r--r--ee4363/mp2/out617
-rw-r--r--ee4363/mp2/output.txt319
-rw-r--r--ee4363/mp2/test_mipspipe.vcd515
3 files changed, 975 insertions, 476 deletions
diff --git a/ee4363/mp2/out b/ee4363/mp2/out
index 21917ca..d1cf046 100644
--- a/ee4363/mp2/out
+++ b/ee4363/mp2/out
@@ -6,349 +6,488 @@
:vpi_module "vhdl_sys";
:vpi_module "v2005_math";
:vpi_module "va_math";
-S_0x557ce3145980 .scope module, "test_mipspipe" "test_mipspipe" 2 8;
+S_0x564ddbdc8770 .scope module, "test_mipspipe" "test_mipspipe" 2 8;
.timescale 0 0;
-v0x557ce3191970_0 .var "clock", 0 0;
-v0x557ce3191a10_0 .var "clock_cycle", 3 0;
-E_0x557ce315b100 .event negedge, v0x557ce31915d0_0;
-S_0x557ce314d3e0 .scope module, "u_mipspipe_mp2" "mipspipe_mp2" 2 14, 3 3 0, S_0x557ce3145980;
+v0x564ddbdfad40_0 .var "clock", 0 0;
+v0x564ddbdfade0_0 .var "clock_cycle", 3 0;
+E_0x564ddbdafec0 .event negedge, v0x564ddbdfa9a0_0;
+S_0x564ddbd98590 .scope module, "u_mipspipe_mp2" "mipspipe_mp2" 2 14, 3 3 0, S_0x564ddbdc8770;
.timescale 0 0;
.port_info 0 /INPUT 1 "clock"
-P_0x557ce314c090 .param/l "ALUop" 0 3 8, C4<000000>;
-P_0x557ce314c0d0 .param/l "BEQ" 0 3 8, C4<000100>;
-P_0x557ce314c110 .param/l "LW" 0 3 8, C4<100011>;
-P_0x557ce314c150 .param/l "SW" 0 3 8, C4<101011>;
-P_0x557ce314c190 .param/l "nop" 0 3 8, C4<00000000000000000000000000100000>;
-L_0x557ce31544c0 .functor AND 1, L_0x557ce31921f0, L_0x557ce31a24a0, C4<1>, C4<1>;
-L_0x557ce311fa40 .functor AND 1, L_0x557ce31544c0, L_0x557ce31a26b0, C4<1>, C4<1>;
-L_0x557ce31a27f0 .functor AND 1, L_0x557ce31a29f0, L_0x557ce31a2c10, C4<1>, C4<1>;
-L_0x557ce311f820 .functor AND 1, L_0x557ce31a27f0, L_0x557ce31a2f40, C4<1>, C4<1>;
-L_0x7f83ba241138 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
-L_0x557ce311f930 .functor OR 1, L_0x7f83ba241138, L_0x557ce311f820, C4<0>, C4<0>;
-L_0x557ce31543f0 .functor BUFZ 32, v0x557ce318f570_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
-v0x557ce316a9a0_0 .net "Ain", 31 0, L_0x557ce31a3330; 1 drivers
-v0x557ce318ee60_0 .net "Bin", 31 0, L_0x557ce31543f0; 1 drivers
-v0x557ce318ef40 .array "DMemory", 1023 0, 31 0;
-v0x557ce318efe0_0 .var "EXMEMALUOut", 31 0;
-v0x557ce318f0c0_0 .var "EXMEMB", 31 0;
-v0x557ce318f1f0_0 .var "EXMEMIR", 31 0;
-v0x557ce318f2d0_0 .net "EXMEMop", 5 0, L_0x557ce3191f30; 1 drivers
-v0x557ce318f3b0_0 .net "EXMEMrd", 4 0, L_0x557ce3191c10; 1 drivers
-v0x557ce318f490_0 .var "IDEXA", 31 0;
-v0x557ce318f570_0 .var "IDEXB", 31 0;
-v0x557ce318f650_0 .var "IDEXIR", 31 0;
-v0x557ce318f730_0 .net "IDEXop", 5 0, L_0x557ce3192100; 1 drivers
-v0x557ce318f810_0 .net "IDEXrs", 4 0, L_0x557ce3191ad0; 1 drivers
-v0x557ce318f8f0_0 .net "IDEXrt", 4 0, L_0x557ce3191b70; 1 drivers
-v0x557ce318f9d0_0 .var "IFIDIR", 31 0;
-v0x557ce318fab0 .array "IMemory", 1023 0, 31 0;
-v0x557ce318fb70_0 .var "MEMWBIR", 31 0;
-v0x557ce318fc50_0 .var "MEMWBValue", 31 0;
-v0x557ce318fd30_0 .net "MEMWBop", 5 0, L_0x557ce3192060; 1 drivers
-v0x557ce318fe10_0 .net "MEMWBrd", 4 0, L_0x557ce3191ce0; 1 drivers
-v0x557ce318fef0_0 .net "MEMWBrt", 4 0, L_0x557ce3191e10; 1 drivers
-v0x557ce318ffd0_0 .var "PC", 31 0;
-v0x557ce31900b0 .array "Regs", 31 0, 31 0;
-v0x557ce3190170_0 .net *"_s16", 0 0, L_0x557ce31921f0; 1 drivers
-v0x557ce3190230_0 .net *"_s18", 31 0, L_0x557ce3192360; 1 drivers
-L_0x7f83ba241018 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
-v0x557ce3190310_0 .net *"_s21", 26 0, L_0x7f83ba241018; 1 drivers
-L_0x7f83ba241060 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
-v0x557ce31903f0_0 .net/2u *"_s22", 31 0, L_0x7f83ba241060; 1 drivers
-v0x557ce31904d0_0 .net *"_s24", 0 0, L_0x557ce31a24a0; 1 drivers
-v0x557ce3190590_0 .net *"_s26", 0 0, L_0x557ce31544c0; 1 drivers
-L_0x7f83ba2410a8 .functor BUFT 1, C4<000000>, C4<0>, C4<0>, C4<0>;
-v0x557ce3190670_0 .net/2u *"_s28", 5 0, L_0x7f83ba2410a8; 1 drivers
-v0x557ce3190750_0 .net *"_s30", 0 0, L_0x557ce31a26b0; 1 drivers
-v0x557ce3190810_0 .net *"_s41", 4 0, L_0x557ce31a2950; 1 drivers
-v0x557ce31908f0_0 .net *"_s42", 0 0, L_0x557ce31a29f0; 1 drivers
-v0x557ce31909b0_0 .net *"_s44", 31 0, L_0x557ce31a2b40; 1 drivers
-L_0x7f83ba2411c8 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
-v0x557ce3190a90_0 .net *"_s47", 26 0, L_0x7f83ba2411c8; 1 drivers
-L_0x7f83ba241210 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
-v0x557ce3190b70_0 .net/2u *"_s48", 31 0, L_0x7f83ba241210; 1 drivers
-v0x557ce3190c50_0 .net *"_s50", 0 0, L_0x557ce31a2c10; 1 drivers
-v0x557ce3190d10_0 .net *"_s52", 0 0, L_0x557ce31a27f0; 1 drivers
-L_0x7f83ba241258 .functor BUFT 1, C4<100011>, C4<0>, C4<0>, C4<0>;
-v0x557ce3190df0_0 .net/2u *"_s54", 5 0, L_0x7f83ba241258; 1 drivers
-v0x557ce3190ed0_0 .net *"_s56", 0 0, L_0x557ce31a2f40; 1 drivers
-v0x557ce3190f90_0 .net *"_s62", 0 0, L_0x557ce311f930; 1 drivers
-v0x557ce3191070_0 .net *"_s64", 31 0, L_0x557ce31a31a0; 1 drivers
-v0x557ce3191150_0 .net "bypassAfromALUinWB", 0 0, L_0x7f83ba241138; 1 drivers
-v0x557ce3191210_0 .net "bypassAfromLWinWB", 0 0, L_0x557ce311f820; 1 drivers
-v0x557ce31912d0_0 .net "bypassAfromMEM", 0 0, L_0x557ce311fa40; 1 drivers
-L_0x7f83ba241180 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
-v0x557ce3191390_0 .net "bypassBfromALUinWB", 0 0, L_0x7f83ba241180; 1 drivers
-L_0x7f83ba2412a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
-v0x557ce3191450_0 .net "bypassBfromLWinWB", 0 0, L_0x7f83ba2412a0; 1 drivers
-L_0x7f83ba2410f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
-v0x557ce3191510_0 .net "bypassBfromMEM", 0 0, L_0x7f83ba2410f0; 1 drivers
-v0x557ce31915d0_0 .net "clock", 0 0, v0x557ce3191970_0; 1 drivers
-v0x557ce3191690_0 .var "i", 5 0;
-v0x557ce3191770_0 .var "j", 10 0;
-v0x557ce3191850_0 .var "k", 10 0;
-E_0x557ce315b3f0 .event posedge, v0x557ce31915d0_0;
-L_0x557ce3191ad0 .part v0x557ce318f650_0, 21, 5;
-L_0x557ce3191b70 .part v0x557ce318f650_0, 16, 5;
-L_0x557ce3191c10 .part v0x557ce318f1f0_0, 11, 5;
-L_0x557ce3191ce0 .part v0x557ce318fb70_0, 11, 5;
-L_0x557ce3191e10 .part v0x557ce318fb70_0, 16, 5;
-L_0x557ce3191f30 .part v0x557ce318f1f0_0, 26, 6;
-L_0x557ce3192060 .part v0x557ce318fb70_0, 26, 6;
-L_0x557ce3192100 .part v0x557ce318f650_0, 26, 6;
-L_0x557ce31921f0 .cmp/eq 5, L_0x557ce3191ad0, L_0x557ce3191c10;
-L_0x557ce3192360 .concat [ 5 27 0 0], L_0x557ce3191ad0, L_0x7f83ba241018;
-L_0x557ce31a24a0 .cmp/ne 32, L_0x557ce3192360, L_0x7f83ba241060;
-L_0x557ce31a26b0 .cmp/eq 6, L_0x557ce3191f30, L_0x7f83ba2410a8;
-L_0x557ce31a2950 .part v0x557ce318fb70_0, 16, 5;
-L_0x557ce31a29f0 .cmp/eq 5, L_0x557ce3191ad0, L_0x557ce31a2950;
-L_0x557ce31a2b40 .concat [ 5 27 0 0], L_0x557ce3191ad0, L_0x7f83ba2411c8;
-L_0x557ce31a2c10 .cmp/ne 32, L_0x557ce31a2b40, L_0x7f83ba241210;
-L_0x557ce31a2f40 .cmp/eq 6, L_0x557ce3192060, L_0x7f83ba241258;
-L_0x557ce31a31a0 .functor MUXZ 32, v0x557ce318f490_0, v0x557ce318fc50_0, L_0x557ce311f930, C4<>;
-L_0x557ce31a3330 .functor MUXZ 32, L_0x557ce31a31a0, v0x557ce318efe0_0, L_0x557ce311fa40, C4<>;
- .scope S_0x557ce314d3e0;
+P_0x564ddbd9f9c0 .param/l "ALUop" 0 3 8, C4<000000>;
+P_0x564ddbd9fa00 .param/l "BEQ" 0 3 8, C4<000100>;
+P_0x564ddbd9fa40 .param/l "LW" 0 3 8, C4<100011>;
+P_0x564ddbd9fa80 .param/l "SW" 0 3 8, C4<101011>;
+P_0x564ddbd9fac0 .param/l "nop" 0 3 8, C4<00000000000000000000000000100000>;
+L_0x564ddbda64c0 .functor AND 1, L_0x564ddbdfb8e0, L_0x564ddbe0bba0, C4<1>, C4<1>;
+L_0x564ddbd71a40 .functor AND 1, L_0x564ddbda64c0, L_0x564ddbe0be30, C4<1>, C4<1>;
+L_0x564ddbd71820 .functor AND 1, L_0x564ddbe0c190, L_0x564ddbe0c3d0, C4<1>, C4<1>;
+L_0x564ddbd71930 .functor AND 1, L_0x564ddbd71820, L_0x564ddbe0c5e0, C4<1>, C4<1>;
+L_0x564ddbda63f0 .functor AND 1, L_0x564ddbe0c330, L_0x564ddbe0c8a0, C4<1>, C4<1>;
+L_0x564ddbdd2e70 .functor AND 1, L_0x564ddbda63f0, L_0x564ddbe0cb30, C4<1>, C4<1>;
+L_0x564ddbdd2ee0 .functor AND 1, L_0x564ddbdd2e70, L_0x564ddbe0cd50, C4<1>, C4<1>;
+L_0x564ddbdfba00 .functor AND 1, L_0x564ddbe0cfb0, L_0x564ddbe0d0e0, C4<1>, C4<1>;
+L_0x564ddbe0d3a0 .functor OR 1, L_0x564ddbdd2ee0, L_0x564ddbdfba00, C4<0>, C4<0>;
+L_0x564ddbe0d780 .functor AND 1, L_0x564ddbe0d4b0, L_0x564ddbe0d5a0, C4<1>, C4<1>;
+L_0x564ddbe0d990 .functor AND 1, L_0x564ddbe0d780, L_0x564ddbe0d8f0, C4<1>, C4<1>;
+L_0x564ddbe0dc90 .functor AND 1, L_0x564ddbe0d990, L_0x564ddbe0daa0, C4<1>, C4<1>;
+L_0x564ddbe0e0b0 .functor AND 1, L_0x564ddbe0de10, L_0x564ddbe0df00, C4<1>, C4<1>;
+L_0x564ddbe0e1c0 .functor OR 1, L_0x564ddbe0dc90, L_0x564ddbe0e0b0, C4<0>, C4<0>;
+L_0x7fe07295a138 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+L_0x564ddbe0dda0 .functor OR 1, L_0x7fe07295a138, L_0x564ddbd71930, C4<0>, C4<0>;
+L_0x7fe07295a180 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+L_0x7fe07295a2a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+L_0x564ddbe0e740 .functor OR 1, L_0x7fe07295a180, L_0x7fe07295a2a0, C4<0>, C4<0>;
+L_0x564ddbe0eec0 .functor AND 1, L_0x564ddbe0e580, L_0x564ddbe0ece0, C4<1>, C4<1>;
+L_0x564ddbe0f470 .functor OR 1, L_0x564ddbe0f0c0, L_0x564ddbe0f2b0, C4<0>, C4<0>;
+L_0x564ddbe0f580 .functor AND 1, L_0x564ddbe0efd0, L_0x564ddbe0f470, C4<1>, C4<1>;
+L_0x564ddbe0f690 .functor OR 1, L_0x564ddbe0eec0, L_0x564ddbe0f580, C4<0>, C4<0>;
+L_0x564ddbe0fc60 .functor OR 1, L_0x564ddbe0f9b0, L_0x564ddbe0fa50, C4<0>, C4<0>;
+L_0x564ddbe0fd70 .functor AND 1, L_0x564ddbe0f4e0, L_0x564ddbe0fc60, C4<1>, C4<1>;
+L_0x564ddbe0ff40 .functor OR 1, L_0x564ddbe0f690, L_0x564ddbe0fd70, C4<0>, C4<0>;
+L_0x564ddbe10050 .functor AND 1, L_0x564ddbe0ea20, L_0x564ddbe0ff40, C4<1>, C4<1>;
+L_0x564ddbe10230 .functor BUFT 32, L_0x564ddbe0e8e0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+v0x564ddbdd1880_0 .net "Ain", 31 0, L_0x564ddbe0e4e0; 1 drivers
+v0x564ddbdc3640_0 .net "Bin", 31 0, L_0x564ddbe10230; 1 drivers
+v0x564ddbdf5160 .array "DMemory", 1023 0, 31 0;
+v0x564ddbdf5200_0 .var "EXMEMALUOut", 31 0;
+v0x564ddbdf52e0_0 .var "EXMEMB", 31 0;
+v0x564ddbdf5410_0 .var "EXMEMIR", 31 0;
+v0x564ddbdf54f0_0 .net "EXMEMop", 5 0, L_0x564ddbdfb300; 1 drivers
+v0x564ddbdf55d0_0 .net "EXMEMrd", 4 0, L_0x564ddbdfafe0; 1 drivers
+v0x564ddbdf56b0_0 .var "IDEXA", 31 0;
+v0x564ddbdf5790_0 .var "IDEXB", 31 0;
+v0x564ddbdf5870_0 .var "IDEXIR", 31 0;
+v0x564ddbdf5950_0 .net "IDEXop", 5 0, L_0x564ddbdfb4d0; 1 drivers
+v0x564ddbdf5a30_0 .net "IDEXrs", 4 0, L_0x564ddbdfaea0; 1 drivers
+v0x564ddbdf5b10_0 .net "IDEXrt", 4 0, L_0x564ddbdfaf40; 1 drivers
+v0x564ddbdf5bf0_0 .var "IFIDIR", 31 0;
+v0x564ddbdf5cd0_0 .net "IFIDop", 5 0, L_0x564ddbdfb840; 1 drivers
+v0x564ddbdf5db0_0 .net "IFIDrs", 4 0, L_0x564ddbdfb5c0; 1 drivers
+v0x564ddbdf5e90_0 .net "IFIDrt", 4 0, L_0x564ddbdfb6c0; 1 drivers
+v0x564ddbdf5f70 .array "IMemory", 1023 0, 31 0;
+v0x564ddbdf6030_0 .var "MEMWBIR", 31 0;
+v0x564ddbdf6110_0 .var "MEMWBValue", 31 0;
+v0x564ddbdf61f0_0 .net "MEMWBop", 5 0, L_0x564ddbdfb430; 1 drivers
+v0x564ddbdf62d0_0 .net "MEMWBrd", 4 0, L_0x564ddbdfb0b0; 1 drivers
+v0x564ddbdf63b0_0 .net "MEMWBrt", 4 0, L_0x564ddbdfb1e0; 1 drivers
+v0x564ddbdf6490_0 .var "PC", 31 0;
+v0x564ddbdf6570 .array "Regs", 31 0, 31 0;
+v0x564ddbdf6630_0 .net "STALL", 0 0, L_0x564ddbe10050; 1 drivers
+v0x564ddbdf66f0_0 .net *"_s100", 0 0, L_0x564ddbe0d4b0; 1 drivers
+L_0x7fe07295a450 .functor BUFT 1, C4<00000000000000000000000000100000>, C4<0>, C4<0>, C4<0>;
+v0x564ddbdf67b0_0 .net/2u *"_s102", 31 0, L_0x7fe07295a450; 1 drivers
+v0x564ddbdf6890_0 .net *"_s104", 0 0, L_0x564ddbe0d5a0; 1 drivers
+v0x564ddbdf6950_0 .net *"_s106", 0 0, L_0x564ddbe0d780; 1 drivers
+v0x564ddbdf6a30_0 .net *"_s108", 0 0, L_0x564ddbe0d8f0; 1 drivers
+v0x564ddbdf6af0_0 .net *"_s110", 0 0, L_0x564ddbe0d990; 1 drivers
+L_0x7fe07295a498 .functor BUFT 1, C4<100011>, C4<0>, C4<0>, C4<0>;
+v0x564ddbdf6bd0_0 .net/2u *"_s112", 5 0, L_0x7fe07295a498; 1 drivers
+v0x564ddbdf6cb0_0 .net *"_s114", 0 0, L_0x564ddbe0daa0; 1 drivers
+v0x564ddbdf6d70_0 .net *"_s116", 0 0, L_0x564ddbe0dc90; 1 drivers
+L_0x7fe07295a4e0 .functor BUFT 1, C4<000000>, C4<0>, C4<0>, C4<0>;
+v0x564ddbdf6e50_0 .net/2u *"_s118", 5 0, L_0x7fe07295a4e0; 1 drivers
+v0x564ddbdf6f30_0 .net *"_s120", 0 0, L_0x564ddbe0de10; 1 drivers
+v0x564ddbdf6ff0_0 .net *"_s122", 0 0, L_0x564ddbe0df00; 1 drivers
+v0x564ddbdf70b0_0 .net *"_s124", 0 0, L_0x564ddbe0e0b0; 1 drivers
+v0x564ddbdf7190_0 .net *"_s128", 0 0, L_0x564ddbe0dda0; 1 drivers
+v0x564ddbdf7270_0 .net *"_s130", 31 0, L_0x564ddbe0e3f0; 1 drivers
+v0x564ddbdf7350_0 .net *"_s134", 0 0, L_0x564ddbe0e740; 1 drivers
+v0x564ddbdf7430_0 .net *"_s136", 31 0, L_0x564ddbe0e8e0; 1 drivers
+L_0x7fe07295a528 .functor BUFT 1, C4<100011>, C4<0>, C4<0>, C4<0>;
+v0x564ddbdf7510_0 .net/2u *"_s140", 5 0, L_0x7fe07295a528; 1 drivers
+v0x564ddbdf75f0_0 .net *"_s142", 0 0, L_0x564ddbe0ea20; 1 drivers
+L_0x7fe07295a570 .functor BUFT 1, C4<100011>, C4<0>, C4<0>, C4<0>;
+v0x564ddbdf76b0_0 .net/2u *"_s144", 5 0, L_0x7fe07295a570; 1 drivers
+v0x564ddbdf7790_0 .net *"_s146", 0 0, L_0x564ddbe0e580; 1 drivers
+v0x564ddbdf7850_0 .net *"_s148", 0 0, L_0x564ddbe0ece0; 1 drivers
+v0x564ddbdf7910_0 .net *"_s150", 0 0, L_0x564ddbe0eec0; 1 drivers
+L_0x7fe07295a5b8 .functor BUFT 1, C4<000000>, C4<0>, C4<0>, C4<0>;
+v0x564ddbdf79d0_0 .net/2u *"_s152", 5 0, L_0x7fe07295a5b8; 1 drivers
+v0x564ddbdf7ab0_0 .net *"_s154", 0 0, L_0x564ddbe0efd0; 1 drivers
+v0x564ddbdf7b70_0 .net *"_s156", 0 0, L_0x564ddbe0f0c0; 1 drivers
+v0x564ddbdf7c30_0 .net *"_s158", 0 0, L_0x564ddbe0f2b0; 1 drivers
+v0x564ddbdf7cf0_0 .net *"_s160", 0 0, L_0x564ddbe0f470; 1 drivers
+v0x564ddbdf7dd0_0 .net *"_s162", 0 0, L_0x564ddbe0f580; 1 drivers
+v0x564ddbdf7e90_0 .net *"_s164", 0 0, L_0x564ddbe0f690; 1 drivers
+L_0x7fe07295a600 .functor BUFT 1, C4<101011>, C4<0>, C4<0>, C4<0>;
+v0x564ddbdf7f70_0 .net/2u *"_s166", 5 0, L_0x7fe07295a600; 1 drivers
+v0x564ddbdf8050_0 .net *"_s168", 0 0, L_0x564ddbe0f4e0; 1 drivers
+v0x564ddbdf8110_0 .net *"_s170", 0 0, L_0x564ddbe0f9b0; 1 drivers
+v0x564ddbdf81d0_0 .net *"_s172", 0 0, L_0x564ddbe0fa50; 1 drivers
+v0x564ddbdf8290_0 .net *"_s174", 0 0, L_0x564ddbe0fc60; 1 drivers
+v0x564ddbdf8370_0 .net *"_s176", 0 0, L_0x564ddbe0fd70; 1 drivers
+v0x564ddbdf8430_0 .net *"_s178", 0 0, L_0x564ddbe0ff40; 1 drivers
+v0x564ddbdf8510_0 .net *"_s22", 0 0, L_0x564ddbdfb8e0; 1 drivers
+v0x564ddbdf89e0_0 .net *"_s24", 31 0, L_0x564ddbdfba70; 1 drivers
+L_0x7fe07295a018 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0x564ddbdf8ac0_0 .net *"_s27", 26 0, L_0x7fe07295a018; 1 drivers
+L_0x7fe07295a060 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0x564ddbdf8ba0_0 .net/2u *"_s28", 31 0, L_0x7fe07295a060; 1 drivers
+v0x564ddbdf8c80_0 .net *"_s30", 0 0, L_0x564ddbe0bba0; 1 drivers
+v0x564ddbdf8d40_0 .net *"_s32", 0 0, L_0x564ddbda64c0; 1 drivers
+L_0x7fe07295a0a8 .functor BUFT 1, C4<000000>, C4<0>, C4<0>, C4<0>;
+v0x564ddbdf8e20_0 .net/2u *"_s34", 5 0, L_0x7fe07295a0a8; 1 drivers
+v0x564ddbdf8f00_0 .net *"_s36", 0 0, L_0x564ddbe0be30; 1 drivers
+v0x564ddbdf8fc0_0 .net *"_s47", 4 0, L_0x564ddbe0c060; 1 drivers
+v0x564ddbdf90a0_0 .net *"_s48", 0 0, L_0x564ddbe0c190; 1 drivers
+v0x564ddbdf9160_0 .net *"_s50", 31 0, L_0x564ddbe0c260; 1 drivers
+L_0x7fe07295a1c8 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0x564ddbdf9240_0 .net *"_s53", 26 0, L_0x7fe07295a1c8; 1 drivers
+L_0x7fe07295a210 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0x564ddbdf9320_0 .net/2u *"_s54", 31 0, L_0x7fe07295a210; 1 drivers
+v0x564ddbdf9400_0 .net *"_s56", 0 0, L_0x564ddbe0c3d0; 1 drivers
+v0x564ddbdf94c0_0 .net *"_s58", 0 0, L_0x564ddbd71820; 1 drivers
+L_0x7fe07295a258 .functor BUFT 1, C4<100011>, C4<0>, C4<0>, C4<0>;
+v0x564ddbdf95a0_0 .net/2u *"_s60", 5 0, L_0x7fe07295a258; 1 drivers
+v0x564ddbdf9680_0 .net *"_s62", 0 0, L_0x564ddbe0c5e0; 1 drivers
+L_0x7fe07295a2e8 .functor BUFT 1, C4<00000000000000000000000000100000>, C4<0>, C4<0>, C4<0>;
+v0x564ddbdf9740_0 .net/2u *"_s68", 31 0, L_0x7fe07295a2e8; 1 drivers
+v0x564ddbdf9820_0 .net *"_s70", 0 0, L_0x564ddbe0c330; 1 drivers
+L_0x7fe07295a330 .functor BUFT 1, C4<00000000000000000000000000100000>, C4<0>, C4<0>, C4<0>;
+v0x564ddbdf98e0_0 .net/2u *"_s72", 31 0, L_0x7fe07295a330; 1 drivers
+v0x564ddbdf99c0_0 .net *"_s74", 0 0, L_0x564ddbe0c8a0; 1 drivers
+v0x564ddbdf9a80_0 .net *"_s76", 0 0, L_0x564ddbda63f0; 1 drivers
+v0x564ddbdf9b60_0 .net *"_s78", 0 0, L_0x564ddbe0cb30; 1 drivers
+v0x564ddbdf9c20_0 .net *"_s80", 0 0, L_0x564ddbdd2e70; 1 drivers
+L_0x7fe07295a378 .functor BUFT 1, C4<100011>, C4<0>, C4<0>, C4<0>;
+v0x564ddbdf9d00_0 .net/2u *"_s82", 5 0, L_0x7fe07295a378; 1 drivers
+v0x564ddbdf9de0_0 .net *"_s84", 0 0, L_0x564ddbe0cd50; 1 drivers
+v0x564ddbdf9ea0_0 .net *"_s86", 0 0, L_0x564ddbdd2ee0; 1 drivers
+L_0x7fe07295a3c0 .functor BUFT 1, C4<000000>, C4<0>, C4<0>, C4<0>;
+v0x564ddbdf9f80_0 .net/2u *"_s88", 5 0, L_0x7fe07295a3c0; 1 drivers
+v0x564ddbdfa060_0 .net *"_s90", 0 0, L_0x564ddbe0cfb0; 1 drivers
+v0x564ddbdfa120_0 .net *"_s92", 0 0, L_0x564ddbe0d0e0; 1 drivers
+v0x564ddbdfa1e0_0 .net *"_s94", 0 0, L_0x564ddbdfba00; 1 drivers
+L_0x7fe07295a408 .functor BUFT 1, C4<00000000000000000000000000100000>, C4<0>, C4<0>, C4<0>;
+v0x564ddbdfa2c0_0 .net/2u *"_s98", 31 0, L_0x7fe07295a408; 1 drivers
+v0x564ddbdfa3a0_0 .net "bypassAfromALUinWB", 0 0, L_0x7fe07295a138; 1 drivers
+v0x564ddbdfa460_0 .net "bypassAfromLWinWB", 0 0, L_0x564ddbd71930; 1 drivers
+v0x564ddbdfa520_0 .net "bypassAfromMEM", 0 0, L_0x564ddbd71a40; 1 drivers
+v0x564ddbdfa5e0_0 .net "bypassBfromALUinWB", 0 0, L_0x7fe07295a180; 1 drivers
+v0x564ddbdfa6a0_0 .net "bypassBfromLWinWB", 0 0, L_0x7fe07295a2a0; 1 drivers
+L_0x7fe07295a0f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0x564ddbdfa760_0 .net "bypassBfromMEM", 0 0, L_0x7fe07295a0f0; 1 drivers
+v0x564ddbdfa820_0 .net "bypassIDEXAfromWB", 0 0, L_0x564ddbe0d3a0; 1 drivers
+v0x564ddbdfa8e0_0 .net "bypassIDEXBfromWB", 0 0, L_0x564ddbe0e1c0; 1 drivers
+v0x564ddbdfa9a0_0 .net "clock", 0 0, v0x564ddbdfad40_0; 1 drivers
+v0x564ddbdfaa60_0 .var "i", 5 0;
+v0x564ddbdfab40_0 .var "j", 10 0;
+v0x564ddbdfac20_0 .var "k", 10 0;
+E_0x564ddbdb01b0 .event posedge, v0x564ddbdfa9a0_0;
+L_0x564ddbdfaea0 .part v0x564ddbdf5870_0, 21, 5;
+L_0x564ddbdfaf40 .part v0x564ddbdf5870_0, 16, 5;
+L_0x564ddbdfafe0 .part v0x564ddbdf5410_0, 11, 5;
+L_0x564ddbdfb0b0 .part v0x564ddbdf6030_0, 11, 5;
+L_0x564ddbdfb1e0 .part v0x564ddbdf6030_0, 16, 5;
+L_0x564ddbdfb300 .part v0x564ddbdf5410_0, 26, 6;
+L_0x564ddbdfb430 .part v0x564ddbdf6030_0, 26, 6;
+L_0x564ddbdfb4d0 .part v0x564ddbdf5870_0, 26, 6;
+L_0x564ddbdfb5c0 .part v0x564ddbdf5bf0_0, 21, 5;
+L_0x564ddbdfb6c0 .part v0x564ddbdf5bf0_0, 16, 5;
+L_0x564ddbdfb840 .part v0x564ddbdf5bf0_0, 26, 6;
+L_0x564ddbdfb8e0 .cmp/eq 5, L_0x564ddbdfaea0, L_0x564ddbdfafe0;
+L_0x564ddbdfba70 .concat [ 5 27 0 0], L_0x564ddbdfaea0, L_0x7fe07295a018;
+L_0x564ddbe0bba0 .cmp/ne 32, L_0x564ddbdfba70, L_0x7fe07295a060;
+L_0x564ddbe0be30 .cmp/eq 6, L_0x564ddbdfb300, L_0x7fe07295a0a8;
+L_0x564ddbe0c060 .part v0x564ddbdf6030_0, 16, 5;
+L_0x564ddbe0c190 .cmp/eq 5, L_0x564ddbdfaea0, L_0x564ddbe0c060;
+L_0x564ddbe0c260 .concat [ 5 27 0 0], L_0x564ddbdfaea0, L_0x7fe07295a1c8;
+L_0x564ddbe0c3d0 .cmp/ne 32, L_0x564ddbe0c260, L_0x7fe07295a210;
+L_0x564ddbe0c5e0 .cmp/eq 6, L_0x564ddbdfb430, L_0x7fe07295a258;
+L_0x564ddbe0c330 .cmp/ne 32, v0x564ddbdf6030_0, L_0x7fe07295a2e8;
+L_0x564ddbe0c8a0 .cmp/ne 32, v0x564ddbdf5bf0_0, L_0x7fe07295a330;
+L_0x564ddbe0cb30 .cmp/eq 5, L_0x564ddbdfb5c0, L_0x564ddbdfb1e0;
+L_0x564ddbe0cd50 .cmp/eq 6, L_0x564ddbdfb430, L_0x7fe07295a378;
+L_0x564ddbe0cfb0 .cmp/eq 6, L_0x564ddbdfb430, L_0x7fe07295a3c0;
+L_0x564ddbe0d0e0 .cmp/eq 5, L_0x564ddbdfb0b0, L_0x564ddbdfb5c0;
+L_0x564ddbe0d4b0 .cmp/ne 32, v0x564ddbdf6030_0, L_0x7fe07295a408;
+L_0x564ddbe0d5a0 .cmp/ne 32, v0x564ddbdf5bf0_0, L_0x7fe07295a450;
+L_0x564ddbe0d8f0 .cmp/eq 5, L_0x564ddbdfb6c0, L_0x564ddbdfb1e0;
+L_0x564ddbe0daa0 .cmp/eq 6, L_0x564ddbdfb430, L_0x7fe07295a498;
+L_0x564ddbe0de10 .cmp/eq 6, L_0x564ddbdfb430, L_0x7fe07295a4e0;
+L_0x564ddbe0df00 .cmp/eq 5, L_0x564ddbdfb0b0, L_0x564ddbdfb6c0;
+L_0x564ddbe0e3f0 .functor MUXZ 32, v0x564ddbdf56b0_0, v0x564ddbdf6110_0, L_0x564ddbe0dda0, C4<>;
+L_0x564ddbe0e4e0 .functor MUXZ 32, L_0x564ddbe0e3f0, v0x564ddbdf5200_0, L_0x564ddbd71a40, C4<>;
+L_0x564ddbe0e8e0 .functor MUXZ 32, v0x564ddbdf5790_0, v0x564ddbdf6110_0, L_0x564ddbe0e740, C4<>;
+L_0x564ddbe0ea20 .cmp/eq 6, L_0x564ddbdfb4d0, L_0x7fe07295a528;
+L_0x564ddbe0e580 .cmp/eq 6, L_0x564ddbdfb840, L_0x7fe07295a570;
+L_0x564ddbe0ece0 .cmp/eq 5, L_0x564ddbdfb5c0, L_0x564ddbdfaf40;
+L_0x564ddbe0efd0 .cmp/eq 6, L_0x564ddbdfb840, L_0x7fe07295a5b8;
+L_0x564ddbe0f0c0 .cmp/eq 5, L_0x564ddbdfb5c0, L_0x564ddbdfaf40;
+L_0x564ddbe0f2b0 .cmp/eq 5, L_0x564ddbdfb6c0, L_0x564ddbdfaf40;
+L_0x564ddbe0f4e0 .cmp/eq 6, L_0x564ddbdfb840, L_0x7fe07295a600;
+L_0x564ddbe0f9b0 .cmp/eq 5, L_0x564ddbdfb5c0, L_0x564ddbdfaf40;
+L_0x564ddbe0fa50 .cmp/eq 5, L_0x564ddbdfb6c0, L_0x564ddbdfaf40;
+ .scope S_0x564ddbd98590;
T_0 ;
%pushi/vec4 0, 0, 32;
- %store/vec4 v0x557ce318ffd0_0, 0, 32;
+ %store/vec4 v0x564ddbdf6490_0, 0, 32;
%pushi/vec4 32, 0, 32;
- %store/vec4 v0x557ce318f9d0_0, 0, 32;
+ %store/vec4 v0x564ddbdf5bf0_0, 0, 32;
%pushi/vec4 32, 0, 32;
- %store/vec4 v0x557ce318f650_0, 0, 32;
+ %store/vec4 v0x564ddbdf5870_0, 0, 32;
%pushi/vec4 32, 0, 32;
- %store/vec4 v0x557ce318f1f0_0, 0, 32;
+ %store/vec4 v0x564ddbdf5410_0, 0, 32;
%pushi/vec4 32, 0, 32;
- %store/vec4 v0x557ce318fb70_0, 0, 32;
+ %store/vec4 v0x564ddbdf6030_0, 0, 32;
%pushi/vec4 0, 0, 6;
- %store/vec4 v0x557ce3191690_0, 0, 6;
+ %store/vec4 v0x564ddbdfaa60_0, 0, 6;
T_0.0 ;
- %load/vec4 v0x557ce3191690_0;
+ %load/vec4 v0x564ddbdfaa60_0;
%pad/u 32;
%cmpi/u 31, 0, 32;
%flag_or 5, 4;
%jmp/0xz T_0.1, 5;
- %load/vec4 v0x557ce3191690_0;
+ %load/vec4 v0x564ddbdfaa60_0;
%pad/u 32;
- %load/vec4 v0x557ce3191690_0;
+ %load/vec4 v0x564ddbdfaa60_0;
%pad/u 7;
%ix/vec4 4;
- %store/vec4a v0x557ce31900b0, 4, 0;
- %load/vec4 v0x557ce3191690_0;
+ %store/vec4a v0x564ddbdf6570, 4, 0;
+ %load/vec4 v0x564ddbdfaa60_0;
%addi 1, 0, 6;
- %store/vec4 v0x557ce3191690_0, 0, 6;
+ %store/vec4 v0x564ddbdfaa60_0, 0, 6;
%jmp T_0.0;
T_0.1 ;
%pushi/vec4 4270112, 0, 32;
%ix/load 4, 0, 0;
%flag_set/imm 4, 0;
- %store/vec4a v0x557ce318fab0, 4, 0;
+ %store/vec4a v0x564ddbdf5f70, 4, 0;
%pushi/vec4 2359492612, 0, 32;
%ix/load 4, 1, 0;
%flag_set/imm 4, 0;
- %store/vec4a v0x557ce318fab0, 4, 0;
+ %store/vec4a v0x564ddbdf5f70, 4, 0;
%pushi/vec4 2896625669, 0, 32;
%ix/load 4, 2, 0;
%flag_set/imm 4, 0;
- %store/vec4a v0x557ce318fab0, 4, 0;
+ %store/vec4a v0x564ddbdf5f70, 4, 0;
%pushi/vec4 6299680, 0, 32;
%ix/load 4, 3, 0;
%flag_set/imm 4, 0;
- %store/vec4a v0x557ce318fab0, 4, 0;
+ %store/vec4a v0x564ddbdf5f70, 4, 0;
%pushi/vec4 17379360, 0, 32;
%ix/load 4, 4, 0;
%flag_set/imm 4, 0;
- %store/vec4a v0x557ce318fab0, 4, 0;
+ %store/vec4a v0x564ddbdf5f70, 4, 0;
%pushi/vec4 2886074380, 0, 32;
%ix/load 4, 5, 0;
%flag_set/imm 4, 0;
- %store/vec4a v0x557ce318fab0, 4, 0;
+ %store/vec4a v0x564ddbdf5f70, 4, 0;
%pushi/vec4 12603424, 0, 32;
%ix/load 4, 6, 0;
%flag_set/imm 4, 0;
- %store/vec4a v0x557ce318fab0, 4, 0;
+ %store/vec4a v0x564ddbdf5f70, 4, 0;
%pushi/vec4 2349531152, 0, 32;
%ix/load 4, 7, 0;
%flag_set/imm 4, 0;
- %store/vec4a v0x557ce318fab0, 4, 0;
+ %store/vec4a v0x564ddbdf5f70, 4, 0;
%pushi/vec4 32, 0, 32;
%ix/load 4, 8, 0;
%flag_set/imm 4, 0;
- %store/vec4a v0x557ce318fab0, 4, 0;
+ %store/vec4a v0x564ddbdf5f70, 4, 0;
%pushi/vec4 2842656, 0, 32;
%ix/load 4, 9, 0;
%flag_set/imm 4, 0;
- %store/vec4a v0x557ce318fab0, 4, 0;
+ %store/vec4a v0x564ddbdf5f70, 4, 0;
%pushi/vec4 10, 0, 11;
- %store/vec4 v0x557ce3191770_0, 0, 11;
+ %store/vec4 v0x564ddbdfab40_0, 0, 11;
T_0.2 ;
- %load/vec4 v0x557ce3191770_0;
+ %load/vec4 v0x564ddbdfab40_0;
%pad/u 32;
%cmpi/u 1023, 0, 32;
%flag_or 5, 4;
%jmp/0xz T_0.3, 5;
%pushi/vec4 32, 0, 32;
- %load/vec4 v0x557ce3191770_0;
+ %load/vec4 v0x564ddbdfab40_0;
%pad/u 12;
%ix/vec4 4;
- %store/vec4a v0x557ce318fab0, 4, 0;
- %load/vec4 v0x557ce3191770_0;
+ %store/vec4a v0x564ddbdf5f70, 4, 0;
+ %load/vec4 v0x564ddbdfab40_0;
%addi 1, 0, 11;
- %store/vec4 v0x557ce3191770_0, 0, 11;
+ %store/vec4 v0x564ddbdfab40_0, 0, 11;
%jmp T_0.2;
T_0.3 ;
%pushi/vec4 0, 0, 32;
%ix/load 4, 0, 0;
%flag_set/imm 4, 0;
- %store/vec4a v0x557ce318ef40, 4, 0;
+ %store/vec4a v0x564ddbdf5160, 4, 0;
%pushi/vec4 4294967295, 0, 32;
%ix/load 4, 1, 0;
%flag_set/imm 4, 0;
- %store/vec4a v0x557ce318ef40, 4, 0;
+ %store/vec4a v0x564ddbdf5160, 4, 0;
%pushi/vec4 0, 0, 32;
%ix/load 4, 2, 0;
%flag_set/imm 4, 0;
- %store/vec4a v0x557ce318ef40, 4, 0;
+ %store/vec4a v0x564ddbdf5160, 4, 0;
%pushi/vec4 0, 0, 32;
%ix/load 4, 3, 0;
%flag_set/imm 4, 0;
- %store/vec4a v0x557ce318ef40, 4, 0;
+ %store/vec4a v0x564ddbdf5160, 4, 0;
%pushi/vec4 4294967294, 0, 32;
%ix/load 4, 4, 0;
%flag_set/imm 4, 0;
- %store/vec4a v0x557ce318ef40, 4, 0;
+ %store/vec4a v0x564ddbdf5160, 4, 0;
%pushi/vec4 5, 0, 11;
- %store/vec4 v0x557ce3191850_0, 0, 11;
+ %store/vec4 v0x564ddbdfac20_0, 0, 11;
T_0.4 ;
- %load/vec4 v0x557ce3191850_0;
+ %load/vec4 v0x564ddbdfac20_0;
%pad/u 32;
%cmpi/u 1023, 0, 32;
%flag_or 5, 4;
%jmp/0xz T_0.5, 5;
%pushi/vec4 0, 0, 32;
- %load/vec4 v0x557ce3191850_0;
+ %load/vec4 v0x564ddbdfac20_0;
%pad/u 12;
%ix/vec4 4;
- %store/vec4a v0x557ce318ef40, 4, 0;
- %load/vec4 v0x557ce3191850_0;
+ %store/vec4a v0x564ddbdf5160, 4, 0;
+ %load/vec4 v0x564ddbdfac20_0;
%addi 1, 0, 11;
- %store/vec4 v0x557ce3191850_0, 0, 11;
+ %store/vec4 v0x564ddbdfac20_0, 0, 11;
%jmp T_0.4;
T_0.5 ;
%end;
.thread T_0;
- .scope S_0x557ce314d3e0;
+ .scope S_0x564ddbd98590;
T_1 ;
- %wait E_0x557ce315b3f0;
- %load/vec4 v0x557ce318ffd0_0;
+ %wait E_0x564ddbdb01b0;
+ %load/vec4 v0x564ddbdf6630_0;
+ %inv;
+ %flag_set/vec4 8;
+ %jmp/0xz T_1.0, 8;
+ %load/vec4 v0x564ddbdf6490_0;
%ix/load 5, 2, 0;
%flag_set/imm 4, 0;
%shiftr 5;
%ix/vec4 4;
- %load/vec4a v0x557ce318fab0, 4;
- %assign/vec4 v0x557ce318f9d0_0, 0;
- %load/vec4 v0x557ce318ffd0_0;
+ %load/vec4a v0x564ddbdf5f70, 4;
+ %assign/vec4 v0x564ddbdf5bf0_0, 0;
+ %load/vec4 v0x564ddbdf6490_0;
%addi 4, 0, 32;
- %assign/vec4 v0x557ce318ffd0_0, 0;
- %load/vec4 v0x557ce318f9d0_0;
+ %assign/vec4 v0x564ddbdf6490_0, 0;
+ %load/vec4 v0x564ddbdfa820_0;
+ %inv;
+ %flag_set/vec4 8;
+ %jmp/0xz T_1.2, 8;
+ %load/vec4 v0x564ddbdf5bf0_0;
%parti/s 5, 21, 6;
%pad/u 7;
%ix/vec4 4;
- %load/vec4a v0x557ce31900b0, 4;
- %assign/vec4 v0x557ce318f490_0, 0;
- %load/vec4 v0x557ce318f9d0_0;
+ %load/vec4a v0x564ddbdf6570, 4;
+ %assign/vec4 v0x564ddbdf56b0_0, 0;
+ %jmp T_1.3;
+T_1.2 ;
+ %load/vec4 v0x564ddbdf6110_0;
+ %assign/vec4 v0x564ddbdf56b0_0, 0;
+T_1.3 ;
+ %load/vec4 v0x564ddbdfa8e0_0;
+ %inv;
+ %flag_set/vec4 8;
+ %jmp/0xz T_1.4, 8;
+ %load/vec4 v0x564ddbdf5bf0_0;
%parti/s 5, 16, 6;
%pad/u 7;
%ix/vec4 4;
- %load/vec4a v0x557ce31900b0, 4;
- %assign/vec4 v0x557ce318f570_0, 0;
- %load/vec4 v0x557ce318f9d0_0;
- %assign/vec4 v0x557ce318f650_0, 0;
- %load/vec4 v0x557ce318f730_0;
+ %load/vec4a v0x564ddbdf6570, 4;
+ %assign/vec4 v0x564ddbdf5790_0, 0;
+ %jmp T_1.5;
+T_1.4 ;
+ %load/vec4 v0x564ddbdf6110_0;
+ %assign/vec4 v0x564ddbdf5790_0, 0;
+T_1.5 ;
+ %load/vec4 v0x564ddbdf5bf0_0;
+ %assign/vec4 v0x564ddbdf5870_0, 0;
+ %jmp T_1.1;
+T_1.0 ;
+ %pushi/vec4 32, 0, 32;
+ %assign/vec4 v0x564ddbdf5870_0, 0;
+T_1.1 ;
+ %load/vec4 v0x564ddbdf5950_0;
%pushi/vec4 35, 0, 6;
%cmp/e;
%flag_get/vec4 4;
- %load/vec4 v0x557ce318f730_0;
+ %load/vec4 v0x564ddbdf5950_0;
%pushi/vec4 43, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%flag_set/vec4 8;
- %jmp/0xz T_1.0, 8;
- %load/vec4 v0x557ce316a9a0_0;
- %load/vec4 v0x557ce318f650_0;
+ %jmp/0xz T_1.6, 8;
+ %load/vec4 v0x564ddbdd1880_0;
+ %load/vec4 v0x564ddbdf5870_0;
%parti/s 1, 15, 5;
%replicate 16;
- %load/vec4 v0x557ce318f650_0;
+ %load/vec4 v0x564ddbdf5870_0;
%parti/s 16, 0, 2;
%concat/vec4; draw_concat_vec4
%add;
- %assign/vec4 v0x557ce318efe0_0, 0;
- %jmp T_1.1;
-T_1.0 ;
- %load/vec4 v0x557ce318f730_0;
+ %assign/vec4 v0x564ddbdf5200_0, 0;
+ %jmp T_1.7;
+T_1.6 ;
+ %load/vec4 v0x564ddbdf5950_0;
%cmpi/e 0, 0, 6;
- %jmp/0xz T_1.2, 4;
- %load/vec4 v0x557ce318f650_0;
+ %jmp/0xz T_1.8, 4;
+ %load/vec4 v0x564ddbdf5870_0;
%parti/s 6, 0, 2;
%dup/vec4;
%pushi/vec4 32, 0, 6;
%cmp/u;
- %jmp/1 T_1.4, 6;
- %jmp T_1.6;
-T_1.4 ;
- %load/vec4 v0x557ce316a9a0_0;
- %load/vec4 v0x557ce318ee60_0;
+ %jmp/1 T_1.10, 6;
+ %jmp T_1.12;
+T_1.10 ;
+ %load/vec4 v0x564ddbdd1880_0;
+ %load/vec4 v0x564ddbdc3640_0;
%add;
- %assign/vec4 v0x557ce318efe0_0, 0;
- %jmp T_1.6;
-T_1.6 ;
+ %assign/vec4 v0x564ddbdf5200_0, 0;
+ %jmp T_1.12;
+T_1.12 ;
%pop/vec4 1;
-T_1.2 ;
-T_1.1 ;
- %load/vec4 v0x557ce318f650_0;
- %assign/vec4 v0x557ce318f1f0_0, 0;
- %load/vec4 v0x557ce318ee60_0;
- %assign/vec4 v0x557ce318f0c0_0, 0;
- %load/vec4 v0x557ce318f2d0_0;
- %cmpi/e 0, 0, 6;
- %jmp/0xz T_1.7, 4;
- %load/vec4 v0x557ce318efe0_0;
- %assign/vec4 v0x557ce318fc50_0, 0;
- %jmp T_1.8;
+T_1.8 ;
T_1.7 ;
- %load/vec4 v0x557ce318f2d0_0;
+ %load/vec4 v0x564ddbdf5870_0;
+ %assign/vec4 v0x564ddbdf5410_0, 0;
+ %load/vec4 v0x564ddbdc3640_0;
+ %assign/vec4 v0x564ddbdf52e0_0, 0;
+ %load/vec4 v0x564ddbdf54f0_0;
+ %cmpi/e 0, 0, 6;
+ %jmp/0xz T_1.13, 4;
+ %load/vec4 v0x564ddbdf5200_0;
+ %assign/vec4 v0x564ddbdf6110_0, 0;
+ %jmp T_1.14;
+T_1.13 ;
+ %load/vec4 v0x564ddbdf54f0_0;
%cmpi/e 35, 0, 6;
- %jmp/0xz T_1.9, 4;
- %load/vec4 v0x557ce318efe0_0;
+ %jmp/0xz T_1.15, 4;
+ %load/vec4 v0x564ddbdf5200_0;
%ix/load 5, 2, 0;
%flag_set/imm 4, 0;
%shiftr 5;
%ix/vec4 4;
- %load/vec4a v0x557ce318ef40, 4;
- %assign/vec4 v0x557ce318fc50_0, 0;
- %jmp T_1.10;
-T_1.9 ;
- %load/vec4 v0x557ce318f2d0_0;
+ %load/vec4a v0x564ddbdf5160, 4;
+ %assign/vec4 v0x564ddbdf6110_0, 0;
+ %jmp T_1.16;
+T_1.15 ;
+ %load/vec4 v0x564ddbdf54f0_0;
%cmpi/e 43, 0, 6;
- %jmp/0xz T_1.11, 4;
- %load/vec4 v0x557ce318f0c0_0;
- %load/vec4 v0x557ce318efe0_0;
+ %jmp/0xz T_1.17, 4;
+ %load/vec4 v0x564ddbdf52e0_0;
+ %load/vec4 v0x564ddbdf5200_0;
%ix/load 4, 2, 0;
%flag_set/imm 4, 0;
%shiftr 4;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
- %assign/vec4/a/d v0x557ce318ef40, 0, 4;
-T_1.11 ;
-T_1.10 ;
-T_1.8 ;
- %load/vec4 v0x557ce318f1f0_0;
- %assign/vec4 v0x557ce318fb70_0, 0;
- %load/vec4 v0x557ce318fd30_0;
+ %assign/vec4/a/d v0x564ddbdf5160, 0, 4;
+T_1.17 ;
+T_1.16 ;
+T_1.14 ;
+ %load/vec4 v0x564ddbdf5410_0;
+ %assign/vec4 v0x564ddbdf6030_0, 0;
+ %load/vec4 v0x564ddbdf61f0_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
- %load/vec4 v0x557ce318fe10_0;
+ %load/vec4 v0x564ddbdf62d0_0;
%pad/u 32;
%pushi/vec4 0, 0, 32;
%cmp/e;
@@ -356,20 +495,20 @@ T_1.8 ;
%inv;
%and;
%flag_set/vec4 8;
- %jmp/0xz T_1.13, 8;
- %load/vec4 v0x557ce318fc50_0;
- %load/vec4 v0x557ce318fe10_0;
+ %jmp/0xz T_1.19, 8;
+ %load/vec4 v0x564ddbdf6110_0;
+ %load/vec4 v0x564ddbdf62d0_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
- %assign/vec4/a/d v0x557ce31900b0, 0, 4;
- %jmp T_1.14;
-T_1.13 ;
- %load/vec4 v0x557ce318fd30_0;
+ %assign/vec4/a/d v0x564ddbdf6570, 0, 4;
+ %jmp T_1.20;
+T_1.19 ;
+ %load/vec4 v0x564ddbdf61f0_0;
%pushi/vec4 35, 0, 6;
%cmp/e;
%flag_get/vec4 4;
- %load/vec4 v0x557ce318fef0_0;
+ %load/vec4 v0x564ddbdf63b0_0;
%pad/u 32;
%pushi/vec4 0, 0, 32;
%cmp/e;
@@ -377,57 +516,57 @@ T_1.13 ;
%inv;
%and;
%flag_set/vec4 8;
- %jmp/0xz T_1.15, 8;
- %load/vec4 v0x557ce318fc50_0;
- %load/vec4 v0x557ce318fef0_0;
+ %jmp/0xz T_1.21, 8;
+ %load/vec4 v0x564ddbdf6110_0;
+ %load/vec4 v0x564ddbdf63b0_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
- %assign/vec4/a/d v0x557ce31900b0, 0, 4;
-T_1.15 ;
-T_1.14 ;
+ %assign/vec4/a/d v0x564ddbdf6570, 0, 4;
+T_1.21 ;
+T_1.20 ;
%jmp T_1;
.thread T_1;
- .scope S_0x557ce3145980;
+ .scope S_0x564ddbdc8770;
T_2 ;
%pushi/vec4 0, 0, 1;
- %store/vec4 v0x557ce3191970_0, 0, 1;
+ %store/vec4 v0x564ddbdfad40_0, 0, 1;
%pushi/vec4 0, 0, 4;
- %store/vec4 v0x557ce3191a10_0, 0, 4;
+ %store/vec4 v0x564ddbdfade0_0, 0, 4;
%delay 160, 0;
%vpi_call 2 20 "$finish" {0 0 0};
%end;
.thread T_2;
- .scope S_0x557ce3145980;
+ .scope S_0x564ddbdc8770;
T_3 ;
%delay 5, 0;
- %load/vec4 v0x557ce3191970_0;
+ %load/vec4 v0x564ddbdfad40_0;
%inv;
- %store/vec4 v0x557ce3191970_0, 0, 1;
+ %store/vec4 v0x564ddbdfad40_0, 0, 1;
%jmp T_3;
.thread T_3;
- .scope S_0x557ce3145980;
+ .scope S_0x564ddbdc8770;
T_4 ;
- %wait E_0x557ce315b3f0;
- %load/vec4 v0x557ce3191a10_0;
+ %wait E_0x564ddbdb01b0;
+ %load/vec4 v0x564ddbdfade0_0;
%addi 1, 0, 4;
- %store/vec4 v0x557ce3191a10_0, 0, 4;
+ %store/vec4 v0x564ddbdfade0_0, 0, 4;
%jmp T_4;
.thread T_4;
- .scope S_0x557ce3145980;
+ .scope S_0x564ddbdc8770;
T_5 ;
- %wait E_0x557ce315b100;
- %vpi_call 2 36 "$display", "\012\012clock cycle = %d", v0x557ce3191a10_0, " (time = %1.0t)", $time {0 0 0};
- %vpi_call 2 37 "$display", "IF/ID registers\012\011 IF/ID.PC+4 = %h, IF/ID.IR = %h \012", v0x557ce318ffd0_0, v0x557ce318f9d0_0 {0 0 0};
- %vpi_call 2 38 "$display", "ID/EX registers\012\011 ID/EX.rs = %d, ID/EX.rt = %d", v0x557ce318f810_0, v0x557ce318f8f0_0, "\012\011 ID/EX.A = %h, ID/EX.B = %h", v0x557ce318f490_0, v0x557ce318f570_0 {0 0 0};
- %vpi_call 2 39 "$display", "\011 ID/EX.op = %h\012", v0x557ce318f730_0 {0 0 0};
- %vpi_call 2 40 "$display", "EX/MEM registers\012\011 EX/MEM.rs = %d, EX/MEM.rt = %d", v0x557ce318f810_0, v0x557ce318f8f0_0, "\012\011 EX/MEM.ALUOut = %h, EX/MEM.ALUout = %h", v0x557ce318efe0_0, v0x557ce318f0c0_0 {0 0 0};
- %vpi_call 2 41 "$display", "\011 EX/MEM.op = %h\012", v0x557ce318f2d0_0 {0 0 0};
- %vpi_call 2 42 "$display", "MEM/WB registers\012\011 MEM/WB.rd = %d, MEM/WB.rt = %d", v0x557ce318fe10_0, v0x557ce318fef0_0, "\012\011 MEM/WB.value = %h", v0x557ce318fc50_0 {0 0 0};
- %vpi_call 2 43 "$display", "\011 EX/MEM.op = %h\012", v0x557ce318fd30_0 {0 0 0};
+ %wait E_0x564ddbdafec0;
+ %vpi_call 2 36 "$display", "\012\012clock cycle = %d", v0x564ddbdfade0_0, " (time = %1.0t)", $time {0 0 0};
+ %vpi_call 2 37 "$display", "IF/ID registers\012\011 IF/ID.PC+4 = %h, IF/ID.IR = %h \012", v0x564ddbdf6490_0, v0x564ddbdf5bf0_0 {0 0 0};
+ %vpi_call 2 38 "$display", "ID/EX registers\012\011 ID/EX.rs = %d, ID/EX.rt = %d", v0x564ddbdf5a30_0, v0x564ddbdf5b10_0, "\012\011 ID/EX.A = %h, ID/EX.B = %h", v0x564ddbdf56b0_0, v0x564ddbdf5790_0 {0 0 0};
+ %vpi_call 2 39 "$display", "\011 ID/EX.op = %h\012", v0x564ddbdf5950_0 {0 0 0};
+ %vpi_call 2 40 "$display", "EX/MEM registers\012\011 EX/MEM.rs = %d, EX/MEM.rt = %d", v0x564ddbdf5a30_0, v0x564ddbdf5b10_0, "\012\011 EX/MEM.ALUOut = %h, EX/MEM.ALUout = %h", v0x564ddbdf5200_0, v0x564ddbdf52e0_0 {0 0 0};
+ %vpi_call 2 41 "$display", "\011 EX/MEM.op = %h\012", v0x564ddbdf54f0_0 {0 0 0};
+ %vpi_call 2 42 "$display", "MEM/WB registers\012\011 MEM/WB.rd = %d, MEM/WB.rt = %d", v0x564ddbdf62d0_0, v0x564ddbdf63b0_0, "\012\011 MEM/WB.value = %h", v0x564ddbdf6110_0 {0 0 0};
+ %vpi_call 2 43 "$display", "\011 EX/MEM.op = %h\012", v0x564ddbdf61f0_0 {0 0 0};
%jmp T_5;
.thread T_5;
- .scope S_0x557ce3145980;
+ .scope S_0x564ddbdc8770;
T_6 ;
%vpi_call 2 49 "$dumpfile", "test_mipspipe.vcd" {0 0 0};
%vpi_call 2 50 "$dumpvars" {0 0 0};
diff --git a/ee4363/mp2/output.txt b/ee4363/mp2/output.txt
new file mode 100644
index 0000000..cefb5c6
--- /dev/null
+++ b/ee4363/mp2/output.txt
@@ -0,0 +1,319 @@
+VCD info: dumpfile test_mipspipe.vcd opened for output.
+
+
+clock cycle = 1 (time = 10)
+IF/ID registers
+ IF/ID.PC+4 = 00000004, IF/ID.IR = 00412820
+
+ID/EX registers
+ ID/EX.rs = 0, ID/EX.rt = 0
+ ID/EX.A = xxxxxxxx, ID/EX.B = xxxxxxxx
+ ID/EX.op = 00
+
+EX/MEM registers
+ EX/MEM.rs = 0, EX/MEM.rt = 0
+ EX/MEM.ALUOut = xxxxxxxx, EX/MEM.ALUout = xxxxxxxx
+ EX/MEM.op = 00
+
+MEM/WB registers
+ MEM/WB.rd = 0, MEM/WB.rt = 0
+ MEM/WB.value = xxxxxxxx
+ EX/MEM.op = 00
+
+
+
+clock cycle = 2 (time = 20)
+IF/ID registers
+ IF/ID.PC+4 = 00000008, IF/ID.IR = 8ca30004
+
+ID/EX registers
+ ID/EX.rs = 2, ID/EX.rt = 1
+ ID/EX.A = 00000002, ID/EX.B = 00000001
+ ID/EX.op = 00
+
+EX/MEM registers
+ EX/MEM.rs = 2, EX/MEM.rt = 1
+ EX/MEM.ALUOut = xxxxxxxx, EX/MEM.ALUout = xxxxxxxx
+ EX/MEM.op = 00
+
+MEM/WB registers
+ MEM/WB.rd = 0, MEM/WB.rt = 0
+ MEM/WB.value = xxxxxxxx
+ EX/MEM.op = 00
+
+
+
+clock cycle = 3 (time = 30)
+IF/ID registers
+ IF/ID.PC+4 = 0000000c, IF/ID.IR = aca70005
+
+ID/EX registers
+ ID/EX.rs = 5, ID/EX.rt = 3
+ ID/EX.A = 00000005, ID/EX.B = 00000003
+ ID/EX.op = 23
+
+EX/MEM registers
+ EX/MEM.rs = 5, EX/MEM.rt = 3
+ EX/MEM.ALUOut = 00000003, EX/MEM.ALUout = 00000001
+ EX/MEM.op = 00
+
+MEM/WB registers
+ MEM/WB.rd = 0, MEM/WB.rt = 0
+ MEM/WB.value = xxxxxxxx
+ EX/MEM.op = 00
+
+
+
+clock cycle = 4 (time = 40)
+IF/ID registers
+ IF/ID.PC+4 = 00000010, IF/ID.IR = 00602020
+
+ID/EX registers
+ ID/EX.rs = 5, ID/EX.rt = 7
+ ID/EX.A = 00000005, ID/EX.B = 00000007
+ ID/EX.op = 2b
+
+EX/MEM registers
+ EX/MEM.rs = 5, EX/MEM.rt = 7
+ EX/MEM.ALUOut = 00000007, EX/MEM.ALUout = 00000003
+ EX/MEM.op = 23
+
+MEM/WB registers
+ MEM/WB.rd = 5, MEM/WB.rt = 1
+ MEM/WB.value = 00000003
+ EX/MEM.op = 00
+
+
+
+clock cycle = 5 (time = 50)
+IF/ID registers
+ IF/ID.PC+4 = 00000014, IF/ID.IR = 01093020
+
+ID/EX registers
+ ID/EX.rs = 3, ID/EX.rt = 0
+ ID/EX.A = 00000003, ID/EX.B = 00000000
+ ID/EX.op = 00
+
+EX/MEM registers
+ EX/MEM.rs = 3, EX/MEM.rt = 0
+ EX/MEM.ALUOut = 0000000a, EX/MEM.ALUout = 00000007
+ EX/MEM.op = 2b
+
+MEM/WB registers
+ MEM/WB.rd = 0, MEM/WB.rt = 3
+ MEM/WB.value = ffffffff
+ EX/MEM.op = 23
+
+
+
+clock cycle = 6 (time = 60)
+IF/ID registers
+ IF/ID.PC+4 = 00000018, IF/ID.IR = ac06000c
+
+ID/EX registers
+ ID/EX.rs = 8, ID/EX.rt = 9
+ ID/EX.A = 00000008, ID/EX.B = 00000009
+ ID/EX.op = 00
+
+EX/MEM registers
+ EX/MEM.rs = 8, EX/MEM.rt = 9
+ EX/MEM.ALUOut = ffffffff, EX/MEM.ALUout = 00000000
+ EX/MEM.op = 00
+
+MEM/WB registers
+ MEM/WB.rd = 0, MEM/WB.rt = 7
+ MEM/WB.value = ffffffff
+ EX/MEM.op = 2b
+
+
+
+clock cycle = 7 (time = 70)
+IF/ID registers
+ IF/ID.PC+4 = 0000001c, IF/ID.IR = 00c05020
+
+ID/EX registers
+ ID/EX.rs = 0, ID/EX.rt = 6
+ ID/EX.A = 00000000, ID/EX.B = 00000006
+ ID/EX.op = 2b
+
+EX/MEM registers
+ EX/MEM.rs = 0, EX/MEM.rt = 6
+ EX/MEM.ALUOut = 00000011, EX/MEM.ALUout = 00000009
+ EX/MEM.op = 00
+
+MEM/WB registers
+ MEM/WB.rd = 4, MEM/WB.rt = 0
+ MEM/WB.value = ffffffff
+ EX/MEM.op = 00
+
+
+
+clock cycle = 8 (time = 80)
+IF/ID registers
+ IF/ID.PC+4 = 00000020, IF/ID.IR = 8c0b0010
+
+ID/EX registers
+ ID/EX.rs = 6, ID/EX.rt = 0
+ ID/EX.A = 00000006, ID/EX.B = 00000000
+ ID/EX.op = 00
+
+EX/MEM registers
+ EX/MEM.rs = 6, EX/MEM.rt = 0
+ EX/MEM.ALUOut = 0000000c, EX/MEM.ALUout = 00000006
+ EX/MEM.op = 2b
+
+MEM/WB registers
+ MEM/WB.rd = 6, MEM/WB.rt = 9
+ MEM/WB.value = 00000011
+ EX/MEM.op = 00
+
+
+
+clock cycle = 9 (time = 90)
+IF/ID registers
+ IF/ID.PC+4 = 00000024, IF/ID.IR = 00000020
+
+ID/EX registers
+ ID/EX.rs = 0, ID/EX.rt = 11
+ ID/EX.A = 00000000, ID/EX.B = 0000000b
+ ID/EX.op = 23
+
+EX/MEM registers
+ EX/MEM.rs = 0, EX/MEM.rt = 11
+ EX/MEM.ALUOut = 00000006, EX/MEM.ALUout = 00000000
+ EX/MEM.op = 00
+
+MEM/WB registers
+ MEM/WB.rd = 0, MEM/WB.rt = 6
+ MEM/WB.value = 00000011
+ EX/MEM.op = 2b
+
+
+
+clock cycle = 10 (time = 100)
+IF/ID registers
+ IF/ID.PC+4 = 00000028, IF/ID.IR = 002b6020
+
+ID/EX registers
+ ID/EX.rs = 0, ID/EX.rt = 0
+ ID/EX.A = 00000000, ID/EX.B = 00000000
+ ID/EX.op = 00
+
+EX/MEM registers
+ EX/MEM.rs = 0, EX/MEM.rt = 0
+ EX/MEM.ALUOut = 00000010, EX/MEM.ALUout = 0000000b
+ EX/MEM.op = 23
+
+MEM/WB registers
+ MEM/WB.rd = 10, MEM/WB.rt = 0
+ MEM/WB.value = 00000006
+ EX/MEM.op = 00
+
+
+
+clock cycle = 11 (time = 110)
+IF/ID registers
+ IF/ID.PC+4 = 0000002c, IF/ID.IR = 00000020
+
+ID/EX registers
+ ID/EX.rs = 1, ID/EX.rt = 11
+ ID/EX.A = 00000001, ID/EX.B = 0000000b
+ ID/EX.op = 00
+
+EX/MEM registers
+ EX/MEM.rs = 1, EX/MEM.rt = 11
+ EX/MEM.ALUOut = 00000000, EX/MEM.ALUout = 00000000
+ EX/MEM.op = 00
+
+MEM/WB registers
+ MEM/WB.rd = 0, MEM/WB.rt = 11
+ MEM/WB.value = fffffffe
+ EX/MEM.op = 23
+
+
+
+clock cycle = 12 (time = 120)
+IF/ID registers
+ IF/ID.PC+4 = 00000030, IF/ID.IR = 00000020
+
+ID/EX registers
+ ID/EX.rs = 0, ID/EX.rt = 0
+ ID/EX.A = 00000000, ID/EX.B = 00000000
+ ID/EX.op = 00
+
+EX/MEM registers
+ EX/MEM.rs = 0, EX/MEM.rt = 0
+ EX/MEM.ALUOut = 0000000c, EX/MEM.ALUout = 0000000b
+ EX/MEM.op = 00
+
+MEM/WB registers
+ MEM/WB.rd = 0, MEM/WB.rt = 0
+ MEM/WB.value = 00000000
+ EX/MEM.op = 00
+
+
+
+clock cycle = 13 (time = 130)
+IF/ID registers
+ IF/ID.PC+4 = 00000034, IF/ID.IR = 00000020
+
+ID/EX registers
+ ID/EX.rs = 0, ID/EX.rt = 0
+ ID/EX.A = 00000000, ID/EX.B = 00000000
+ ID/EX.op = 00
+
+EX/MEM registers
+ EX/MEM.rs = 0, EX/MEM.rt = 0
+ EX/MEM.ALUOut = 00000000, EX/MEM.ALUout = 00000000
+ EX/MEM.op = 00
+
+MEM/WB registers
+ MEM/WB.rd = 12, MEM/WB.rt = 11
+ MEM/WB.value = 0000000c
+ EX/MEM.op = 00
+
+
+
+clock cycle = 14 (time = 140)
+IF/ID registers
+ IF/ID.PC+4 = 00000038, IF/ID.IR = 00000020
+
+ID/EX registers
+ ID/EX.rs = 0, ID/EX.rt = 0
+ ID/EX.A = 00000000, ID/EX.B = 00000000
+ ID/EX.op = 00
+
+EX/MEM registers
+ EX/MEM.rs = 0, EX/MEM.rt = 0
+ EX/MEM.ALUOut = 00000000, EX/MEM.ALUout = 00000000
+ EX/MEM.op = 00
+
+MEM/WB registers
+ MEM/WB.rd = 0, MEM/WB.rt = 0
+ MEM/WB.value = 00000000
+ EX/MEM.op = 00
+
+
+
+clock cycle = 15 (time = 150)
+IF/ID registers
+ IF/ID.PC+4 = 0000003c, IF/ID.IR = 00000020
+
+ID/EX registers
+ ID/EX.rs = 0, ID/EX.rt = 0
+ ID/EX.A = 00000000, ID/EX.B = 00000000
+ ID/EX.op = 00
+
+EX/MEM registers
+ EX/MEM.rs = 0, EX/MEM.rt = 0
+ EX/MEM.ALUOut = 00000000, EX/MEM.ALUout = 00000000
+ EX/MEM.op = 00
+
+MEM/WB registers
+ MEM/WB.rd = 0, MEM/WB.rt = 0
+ MEM/WB.value = 00000000
+ EX/MEM.op = 00
+
+
+
+clock cycle = 0 (time = 160)
diff --git a/ee4363/mp2/test_mipspipe.vcd b/ee4363/mp2/test_mipspipe.vcd
index b75650b..dedc19b 100644
--- a/ee4363/mp2/test_mipspipe.vcd
+++ b/ee4363/mp2/test_mipspipe.vcd
@@ -1,5 +1,5 @@
$date
- Thu Dec 17 11:20:12 2020
+ Fri Dec 18 19:14:31 2020
$end
$version
Icarus Verilog
@@ -12,62 +12,74 @@ $var reg 1 ! clock $end
$var reg 4 " clock_cycle [3:0] $end
$scope module u_mipspipe_mp2 $end
$var wire 32 # Bin [31:0] $end
-$var wire 1 $ bypassAfromALUinWB $end
-$var wire 1 % bypassAfromLWinWB $end
-$var wire 1 & bypassAfromMEM $end
-$var wire 1 ' bypassBfromALUinWB $end
-$var wire 1 ( bypassBfromLWinWB $end
-$var wire 1 ) bypassBfromMEM $end
+$var wire 1 $ STALL $end
+$var wire 1 % bypassAfromALUinWB $end
+$var wire 1 & bypassAfromLWinWB $end
+$var wire 1 ' bypassAfromMEM $end
+$var wire 1 ( bypassBfromALUinWB $end
+$var wire 1 ) bypassBfromLWinWB $end
+$var wire 1 * bypassBfromMEM $end
+$var wire 1 + bypassIDEXAfromWB $end
+$var wire 1 , bypassIDEXBfromWB $end
$var wire 1 ! clock $end
-$var wire 5 * MEMWBrt [4:0] $end
-$var wire 5 + MEMWBrd [4:0] $end
-$var wire 6 , MEMWBop [5:0] $end
-$var wire 5 - IDEXrt [4:0] $end
-$var wire 5 . IDEXrs [4:0] $end
-$var wire 6 / IDEXop [5:0] $end
-$var wire 5 0 EXMEMrd [4:0] $end
-$var wire 6 1 EXMEMop [5:0] $end
-$var wire 32 2 Ain [31:0] $end
-$var reg 32 3 EXMEMALUOut [31:0] $end
-$var reg 32 4 EXMEMB [31:0] $end
-$var reg 32 5 EXMEMIR [31:0] $end
-$var reg 32 6 IDEXA [31:0] $end
-$var reg 32 7 IDEXB [31:0] $end
-$var reg 32 8 IDEXIR [31:0] $end
-$var reg 32 9 IFIDIR [31:0] $end
-$var reg 32 : MEMWBIR [31:0] $end
-$var reg 32 ; MEMWBValue [31:0] $end
-$var reg 32 < PC [31:0] $end
-$var reg 6 = i [5:0] $end
-$var reg 11 > j [10:0] $end
-$var reg 11 ? k [10:0] $end
+$var wire 5 - MEMWBrt [4:0] $end
+$var wire 5 . MEMWBrd [4:0] $end
+$var wire 6 / MEMWBop [5:0] $end
+$var wire 5 0 IFIDrt [4:0] $end
+$var wire 5 1 IFIDrs [4:0] $end
+$var wire 6 2 IFIDop [5:0] $end
+$var wire 5 3 IDEXrt [4:0] $end
+$var wire 5 4 IDEXrs [4:0] $end
+$var wire 6 5 IDEXop [5:0] $end
+$var wire 5 6 EXMEMrd [4:0] $end
+$var wire 6 7 EXMEMop [5:0] $end
+$var wire 32 8 Ain [31:0] $end
+$var reg 32 9 EXMEMALUOut [31:0] $end
+$var reg 32 : EXMEMB [31:0] $end
+$var reg 32 ; EXMEMIR [31:0] $end
+$var reg 32 < IDEXA [31:0] $end
+$var reg 32 = IDEXB [31:0] $end
+$var reg 32 > IDEXIR [31:0] $end
+$var reg 32 ? IFIDIR [31:0] $end
+$var reg 32 @ MEMWBIR [31:0] $end
+$var reg 32 A MEMWBValue [31:0] $end
+$var reg 32 B PC [31:0] $end
+$var reg 6 C i [5:0] $end
+$var reg 11 D j [10:0] $end
+$var reg 11 E k [10:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
-b10000000000 ?
-b10000000000 >
-b100000 =
-b0 <
-bx ;
-b100000 :
-b100000 9
-b100000 8
-bx 7
-bx 6
-b100000 5
-bx 4
-bx 3
-bx 2
+b10000000000 E
+b10000000000 D
+b100000 C
+b0 B
+bx A
+b100000 @
+b100000 ?
+b100000 >
+bx =
+bx <
+b100000 ;
+bx :
+bx 9
+bx 8
+b0 7
+b0 6
+b0 5
+b0 4
+b0 3
+b0 2
b0 1
b0 0
b0 /
b0 .
b0 -
-b0 ,
-b0 +
-b0 *
+1,
+1+
+0*
0)
0(
0'
@@ -79,293 +91,322 @@ b0 "
0!
$end
#5
-b0 2
-b0 #
-b0 7
-b0 6
-b100 <
-b10000010010100000100000 9
+0+
+0,
+b10 1
+b1 0
+b100 B
+b10000010010100000100000 ?
b1 "
1!
#10
0!
#15
-b10 2
-b10 .
-b1 -
-b0 4
-b0 3
-b10000010010100000100000 8
+b10 8
+b10 4
+b1 3
b1 #
-b1 7
-b10 6
-b1000 <
-b10001100101000110000000000000100 9
+b101 1
+b11 0
+b100011 2
+b10000010010100000100000 >
+b1 =
+b10 <
+b1000 B
+b10001100101000110000000000000100 ?
b10 "
1!
#20
0!
#25
-1&
-b11 2
-b101 0
-b101 .
-b11 -
-b100011 /
-b0 ;
-b1 4
-b10000010010100000100000 5
+1'
+b11 8
+b101 6
+b101 4
b11 3
-b10001100101000110000000000000100 8
+b100011 5
b11 #
-b11 7
-b101 6
-b1100 <
-b10101100101001110000000000000101 9
+b111 0
+b101011 2
+b1 :
+b10000010010100000100000 ;
+b11 9
+b10001100101000110000000000000100 >
+b11 =
+b101 <
+b1100 B
+b10101100101001110000000000000101 ?
b11 "
1!
#30
0!
#35
-0&
-b101 +
-b1 *
-b0 0
-b100011 1
-b101 2
-b111 -
-b101011 /
-b10000010010100000100000 :
-b11 ;
-b11 4
-b10001100101000110000000000000100 5
+0'
+b101 .
+b1 -
+b0 6
+b100011 7
+b101 8
b111 3
-b10101100101001110000000000000101 8
+b101011 5
b111 #
-b111 7
-b10000 <
-b11000000010000000100000 9
+b11 1
+b0 0
+b0 2
+b10000010010100000100000 @
+b11 A
+b11 :
+b10001100101000110000000000000100 ;
+b111 9
+b10101100101001110000000000000101 >
+b111 =
+b10000 B
+b11000000010000000100000 ?
b100 "
1!
#40
0!
#45
-1%
-b11111111111111111111111111111111 2
-b0 +
-b11 *
-b100011 ,
-b101011 1
-b11 .
-b0 -
-b0 /
-b10001100101000110000000000000100 :
-b11111111111111111111111111111111 ;
-b111 4
-b10101100101001110000000000000101 5
-b1010 3
-b11000000010000000100000 8
+1&
+b11111111111111111111111111111111 8
+b0 .
+b11 -
+b100011 /
+b101011 7
+b11 4
+b0 3
+b0 5
b0 #
-b0 7
-b11 6
-b10100 <
-b1000010010011000000100000 9
+b1000 1
+b1001 0
+b10001100101000110000000000000100 @
+b11111111111111111111111111111111 A
+b111 :
+b10101100101001110000000000000101 ;
+b1010 9
+b11000000010000000100000 >
+b0 =
+b11 <
+b10100 B
+b1000010010011000000100000 ?
b101 "
1!
#50
0!
#55
-b1000 2
-0%
-b111 *
-b101011 ,
-b100 0
-b0 1
-b1000 .
-b1001 -
-b10101100101001110000000000000101 :
-b0 4
-b11000000010000000100000 5
-b11111111111111111111111111111111 3
-b1000010010011000000100000 8
+b1000 8
+0&
+b111 -
+b101011 /
+b100 6
+b0 7
+b1000 4
+b1001 3
b1001 #
-b1001 7
-b1000 6
-b11000 <
-b10101100000001100000000000001100 9
+b0 1
+b110 0
+b101011 2
+b10101100101001110000000000000101 @
+b0 :
+b11000000010000000100000 ;
+b11111111111111111111111111111111 9
+b1000010010011000000100000 >
+b1001 =
+b1000 <
+b11000 B
+b10101100000001100000000000001100 ?
b110 "
1!
#60
0!
#65
-b0 2
-b100 +
-b0 *
-b0 ,
-b110 0
-b0 .
-b110 -
-b101011 /
-b11000000010000000100000 :
-b1001 4
-b1000010010011000000100000 5
-b10001 3
-b10101100000001100000000000001100 8
+b0 8
+b100 .
+b0 -
+b0 /
+b110 6
+b0 4
+b110 3
+b101011 5
b110 #
-b110 7
-b0 6
-b11100 <
-b110000000101000000100000 9
+b110 1
+b0 0
+b0 2
+b11000000010000000100000 @
+b1001 :
+b1000010010011000000100000 ;
+b10001 9
+b10101100000001100000000000001100 >
+b110 =
+b0 <
+b11100 B
+b110000000101000000100000 ?
b111 "
1!
#70
0!
#75
-b110 2
-b110 +
-b1001 *
-b0 0
-b101011 1
+b110 8
b110 .
-b0 -
-b0 /
-b1000010010011000000100000 :
-b10001 ;
+b1001 -
+b0 6
+b101011 7
b110 4
-b10101100000001100000000000001100 5
-b1100 3
-b110000000101000000100000 8
+b0 3
+b0 5
b0 #
-b0 7
-b110 6
-b100000 <
-b10001100000010110000000000010000 9
+b0 1
+b1011 0
+b100011 2
+b1000010010011000000100000 @
+b10001 A
+b110 :
+b10101100000001100000000000001100 ;
+b1100 9
+b110000000101000000100000 >
+b0 =
+b110 <
+b100000 B
+b10001100000010110000000000010000 ?
b1000 "
1!
#80
0!
#85
-b0 2
-b0 +
-b110 *
-b101011 ,
-b1010 0
-b0 1
+0$
+b0 8
b0 .
-b1011 -
-b100011 /
-b10101100000001100000000000001100 :
+b110 -
+b101011 /
+b1010 6
+b0 7
b0 4
-b110000000101000000100000 5
-b110 3
-b10001100000010110000000000010000 8
+b1011 3
+b100011 5
b1011 #
-b1011 7
-b0 6
-b100100 <
-b100000 9
+b0 0
+b0 2
+b10101100000001100000000000001100 @
+b0 :
+b110000000101000000100000 ;
+b110 9
+b10001100000010110000000000010000 >
+b1011 =
+b0 <
+b100100 B
+b100000 ?
b1001 "
1!
#90
0!
#95
-b1010 +
-b0 *
-b0 ,
-b0 0
-b100011 1
+b1010 .
b0 -
b0 /
-b110000000101000000100000 :
-b110 ;
-b1011 4
-b10001100000010110000000000010000 5
-b10000 3
-b100000 8
+b0 6
+b100011 7
+b0 3
+b0 5
b0 #
-b0 7
-b101000 <
-b1010110110000000100000 9
+b1 1
+b1011 0
+b110000000101000000100000 @
+b110 A
+b1011 :
+b10001100000010110000000000010000 ;
+b10000 9
+b100000 >
+b0 =
+b101000 B
+b1010110110000000100000 ?
b1010 "
1!
#100
0!
#105
-b1 2
-b0 +
-b1011 *
-b100011 ,
-b0 1
-b1 .
+b1 8
+b0 .
b1011 -
-b10001100000010110000000000010000 :
-b11111111111111111111111111111110 ;
-b0 4
-b100000 5
-b0 3
-b1010110110000000100000 8
+b100011 /
+b0 7
+b1 4
+b1011 3
b1011 #
-b1011 7
-b1 6
-b101100 <
-b100000 9
+b0 1
+b0 0
+b10001100000010110000000000010000 @
+b11111111111111111111111111111110 A
+b0 :
+b100000 ;
+b0 9
+b1010110110000000100000 >
+b1011 =
+b1 <
+b101100 B
+b100000 ?
b1011 "
1!
#110
0!
#115
-b0 2
-b0 *
-b0 ,
-b1100 0
-b0 .
+1+
+1,
+b0 8
b0 -
-b100000 :
-b0 ;
-b1011 4
-b1010110110000000100000 5
-b1100 3
-b100000 8
+b0 /
+b1100 6
+b0 4
+b0 3
b0 #
-b0 7
-b0 6
-b110000 <
+b100000 @
+b0 A
+b1011 :
+b1010110110000000100000 ;
+b1100 9
+b100000 >
+b0 =
+b0 <
+b110000 B
b1100 "
1!
#120
0!
#125
-b1100 +
-b1011 *
-b0 0
-b1010110110000000100000 :
-b1100 ;
-b0 4
-b100000 5
-b0 3
-b110100 <
+0+
+0,
+b1100 .
+b1011 -
+b0 6
+b1010110110000000100000 @
+b1100 A
+b0 :
+b100000 ;
+b0 9
+b110100 B
b1101 "
1!
#130
0!
#135
-b0 +
-b0 *
-b100000 :
-b0 ;
-b111000 <
+1+
+1,
+b0 .
+b0 -
+b100000 @
+b0 A
+b111000 B
b1110 "
1!
#140
0!
#145
-b111100 <
+b111100 B
b1111 "
1!
#150
0!
#155
-b1000000 <
+b1000000 B
b0 "
1!
#160
generated by cgit v1.2.3 (git 2.46.0) at 2024-11-23 13:49:27 +0000