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|
$date
Thu Dec 3 09:43:49 2020
$end
$version
Icarus Verilog
$end
$timescale
100ps
$end
$scope module test_mipsalu $end
$var wire 1 ! Zero $end
$var wire 32 " ALUOut [31:0] $end
$var reg 32 # A [31:0] $end
$var reg 4 $ ALUctl [3:0] $end
$var reg 32 % B [31:0] $end
$scope module U0 $end
$var wire 32 & A [31:0] $end
$var wire 4 ' ALUctl [3:0] $end
$var wire 32 ( B [31:0] $end
$var wire 1 ! Zero $end
$var reg 32 ) ALUOut [31:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b0 )
b1 (
bx '
b1111 &
b1 %
bx $
b1111 #
b0 "
1!
$end
#100
0!
b1 "
b1 )
b0 $
b0 '
#200
b1111 "
b1111 )
b1 $
b1 '
#300
b10000 "
b10000 )
b10 $
b10 '
#400
b1110 "
b1110 )
b110 $
b110 '
#500
|
