get rid of that trash

4 files changed, 866 insertions, 0 deletions

diff --git a/OLD/ee4363/mp1/mp12/mipspipe.v b/OLD/ee4363/mp1/mp12/mipspipe.v
new file mode 100644
index 0000000..41d244d
--- /dev/null
+++ b/OLD/ee4363/mp1/mp12/mipspipe.v
@@ -0,0 +1,101 @@
+// Incomplete behavioral model of MIPS pipeline
+
+module mipspipe(clock);
+   // in_out
+   input clock;
+
+   // Instruction opcodes
+   parameter LW = 6'b100011, SW = 6'b101011, BEQ = 6'b000100, nop = 32'b00000_100000, ALUop = 6'b0; 
+   reg [31:0] PC, // Program counter
+		  Regs[0:31],  // Register file
+			  IMemory[0:1023], DMemory[0:1023], // Instruction and data memories
+              IFIDIR, IDEXA, IDEXB, IDEXIR, EXMEMIR, EXMEMB, // pipeline latches
+              EXMEMALUOut, MEMWBValue, MEMWBIR; // pipeline latches
+
+   wire [4:0] IDEXrs, IDEXrt, EXMEMrd, MEMWBrd, MEMWBrt; // fields of pipeline latches
+   wire [5:0] EXMEMop, MEMWBop, IDEXop; // opcodes
+   wire [31:0] Ain, Bin; // ALU inputs
+
+   // Define fields of pipeline latches
+   assign IDEXrs = IDEXIR[25:21]; // rs field
+   assign IDEXrt = IDEXIR[20:16]; // rt field
+   assign EXMEMrd = EXMEMIR[15:11]; // rd field
+   assign MEMWBrd = MEMWBIR[15:11]; // rd field
+   assign MEMWBrt = MEMWBIR[20:16]; // rt field -- for loads
+   assign EXMEMop = EXMEMIR[31:26]; // opcode
+   assign MEMWBop = MEMWBIR[31:26]; // opcode
+   assign IDEXop = IDEXIR[31:26]; // opcode
+
+   // Inputs to the ALU come directly from the ID/EX pipeline latches
+   assign Ain = IDEXA;
+   assign Bin = IDEXB;
+   reg [5:0] i; //used to initialize registers
+   reg [10:0] j,k; //used to initialize registers
+
+   initial begin
+      PC = 0;
+      IFIDIR = nop; 
+      IDEXIR = nop; 
+      EXMEMIR = nop; 
+      MEMWBIR = nop; // no-ops placed in pipeline latches
+      // test some instructions
+      for (i=0;i<=31;i=i+1) Regs[i] = i; // initialize registers
+      IMemory[0] = 32'h00412820; // ADD OPCODE: 000000 00010 00001 00101 00000 100000
+      IMemory[1] = nop;
+      IMemory[2] = nop;
+      IMemory[3] = nop;
+      IMemory[4] = 32'h8CA30004; // First LW:   100011 00101 00011 00000 00000 000100
+      IMemory[5] = 32'h8C420000; // Second LW:  100011 00010 00010 00000 00000 000000
+      IMemory[6] = nop;
+      IMemory[7] = nop;
+      IMemory[8] = 32'h00A31825; // OR OPCODE:  000000 00101 00011 00011 00000 100101
+      IMemory[9] = nop;
+      IMemory[10] =nop;
+      IMemory[11] = nop;
+      IMemory[12] = 32'hACA30000; // SW:         101011 00101 00011 00000 00000 000000
+      for (j=13;j<=1023;j=j+1) IMemory[j] = nop;
+      DMemory[0] = 32'h00000000;
+      DMemory[1] = 32'hffffffff;
+      for (k=2;k<=1023;k=k+1) DMemory[k] = 0;
+   end
+   
+   always @ (posedge clock) 
+   begin
+      // FETCH: Fetch instruction & update PC
+      IFIDIR <= IMemory[PC>>2];
+	  PC <= PC + 4;
+    
+      // DECODE: Read registers 
+      IDEXA <= Regs[IFIDIR[25:21]]; 
+      IDEXB <= Regs[IFIDIR[20:16]]; // get two registers
+      
+	  IDEXIR <= IFIDIR; // pass along IR
+      
+      // EX: Address calculation or ALU operation
+      if ((IDEXop==LW) |(IDEXop==SW)) // address calculation
+         EXMEMALUOut <= IDEXA +{{16{IDEXIR[15]}}, IDEXIR[15:0]};
+      else if (IDEXop==ALUop) begin // ALU operation
+         case (IDEXIR[5:0]) // R-type instruction
+           32: EXMEMALUOut <= Ain + Bin; // add operation
+           37: EXMEMALUOut <= Ain | Bin; //or
+           default: ; // other R-type operations [to be implemented]
+         endcase
+      end
+   
+      EXMEMIR <= IDEXIR; EXMEMB <= IDEXB; //pass along the IR & B
+   
+      // MEM 
+      if (EXMEMop==ALUop) MEMWBValue <= EXMEMALUOut; //pass along ALU result
+      else if (EXMEMop == LW) MEMWBValue <= DMemory[EXMEMALUOut>>2]; // load
+      else if (EXMEMop == SW) DMemory[EXMEMALUOut>>2] <=EXMEMB; // store
+   
+      MEMWBIR <= EXMEMIR; //pass along IR
+   
+      // WB 
+      if ((MEMWBop==ALUop) & (MEMWBrd != 0)) // update registers if ALU operation and destination not 0
+		Regs[MEMWBrd] <= MEMWBValue; // ALU operation
+      else if ((MEMWBop == LW)& (MEMWBrt != 0)) // Update registers if load and destination not 0
+		Regs[MEMWBrt] <= MEMWBValue;
+    end
+
+endmodule
diff --git a/OLD/ee4363/mp1/mp12/out b/OLD/ee4363/mp1/mp12/out
new file mode 100644
index 0000000..9bb25bb
--- /dev/null
+++ b/OLD/ee4363/mp1/mp12/out
@@ -0,0 +1,401 @@
+#! /usr/bin/vvp
+:ivl_version "10.3 (stable)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "system";
+:vpi_module "vhdl_sys";
+:vpi_module "v2005_math";
+:vpi_module "va_math";
+S_0x55b4011cce40 .scope module, "test_mipspipe" "test_mipspipe" 2 8;
+ .timescale 0 0;
+v0x55b401210350_0 .var "clock", 0 0;
+v0x55b4012103f0_0 .var "clock_cycle", 3 0;
+E_0x55b4011e0f80 .event negedge, v0x55b40120ffb0_0;
+S_0x55b4011cc9a0 .scope module, "u_mipspipe" "mipspipe" 2 14, 3 3 0, S_0x55b4011cce40;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "clock"
+P_0x55b4011cd2e0 .param/l "ALUop" 0 3 8, C4<000000>;
+P_0x55b4011cd320 .param/l "BEQ" 0 3 8, C4<000100>;
+P_0x55b4011cd360 .param/l "LW" 0 3 8, C4<100011>;
+P_0x55b4011cd3a0 .param/l "SW" 0 3 8, C4<101011>;
+P_0x55b4011cd3e0 .param/l "nop" 0 3 8, C4<00000000000000000000000000100000>;
+L_0x55b4011a7a40 .functor BUFZ 32, v0x55b40120f2d0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+L_0x55b4011a7820 .functor BUFZ 32, v0x55b40120f3b0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+v0x55b4011d6de0_0 .net "Ain", 31 0, L_0x55b4011a7a40;  1 drivers
+v0x55b40120eca0_0 .net "Bin", 31 0, L_0x55b4011a7820;  1 drivers
+v0x55b40120ed80 .array "DMemory", 1023 0, 31 0;
+v0x55b40120ee20_0 .var "EXMEMALUOut", 31 0;
+v0x55b40120ef00_0 .var "EXMEMB", 31 0;
+v0x55b40120f030_0 .var "EXMEMIR", 31 0;
+v0x55b40120f110_0 .net "EXMEMop", 5 0, L_0x55b401210910;  1 drivers
+v0x55b40120f1f0_0 .net "EXMEMrd", 4 0, L_0x55b4012105f0;  1 drivers
+v0x55b40120f2d0_0 .var "IDEXA", 31 0;
+v0x55b40120f3b0_0 .var "IDEXB", 31 0;
+v0x55b40120f490_0 .var "IDEXIR", 31 0;
+v0x55b40120f570_0 .net "IDEXop", 5 0, L_0x55b401210ae0;  1 drivers
+v0x55b40120f650_0 .net "IDEXrs", 4 0, L_0x55b4012104b0;  1 drivers
+v0x55b40120f730_0 .net "IDEXrt", 4 0, L_0x55b401210550;  1 drivers
+v0x55b40120f810_0 .var "IFIDIR", 31 0;
+v0x55b40120f8f0 .array "IMemory", 1023 0, 31 0;
+v0x55b40120f9b0_0 .var "MEMWBIR", 31 0;
+v0x55b40120fa90_0 .var "MEMWBValue", 31 0;
+v0x55b40120fb70_0 .net "MEMWBop", 5 0, L_0x55b401210a40;  1 drivers
+v0x55b40120fc50_0 .net "MEMWBrd", 4 0, L_0x55b4012106c0;  1 drivers
+v0x55b40120fd30_0 .net "MEMWBrt", 4 0, L_0x55b4012107f0;  1 drivers
+v0x55b40120fe10_0 .var "PC", 31 0;
+v0x55b40120fef0 .array "Regs", 31 0, 31 0;
+v0x55b40120ffb0_0 .net "clock", 0 0, v0x55b401210350_0;  1 drivers
+v0x55b401210070_0 .var "i", 5 0;
+v0x55b401210150_0 .var "j", 10 0;
+v0x55b401210230_0 .var "k", 10 0;
+E_0x55b4011e1270 .event posedge, v0x55b40120ffb0_0;
+L_0x55b4012104b0 .part v0x55b40120f490_0, 21, 5;
+L_0x55b401210550 .part v0x55b40120f490_0, 16, 5;
+L_0x55b4012105f0 .part v0x55b40120f030_0, 11, 5;
+L_0x55b4012106c0 .part v0x55b40120f9b0_0, 11, 5;
+L_0x55b4012107f0 .part v0x55b40120f9b0_0, 16, 5;
+L_0x55b401210910 .part v0x55b40120f030_0, 26, 6;
+L_0x55b401210a40 .part v0x55b40120f9b0_0, 26, 6;
+L_0x55b401210ae0 .part v0x55b40120f490_0, 26, 6;
+    .scope S_0x55b4011cc9a0;
+T_0 ;
+    %pushi/vec4 0, 0, 32;
+    %store/vec4 v0x55b40120fe10_0, 0, 32;
+    %pushi/vec4 32, 0, 32;
+    %store/vec4 v0x55b40120f810_0, 0, 32;
+    %pushi/vec4 32, 0, 32;
+    %store/vec4 v0x55b40120f490_0, 0, 32;
+    %pushi/vec4 32, 0, 32;
+    %store/vec4 v0x55b40120f030_0, 0, 32;
+    %pushi/vec4 32, 0, 32;
+    %store/vec4 v0x55b40120f9b0_0, 0, 32;
+    %pushi/vec4 0, 0, 6;
+    %store/vec4 v0x55b401210070_0, 0, 6;
+T_0.0 ;
+    %load/vec4 v0x55b401210070_0;
+    %pad/u 32;
+    %cmpi/u 31, 0, 32;
+    %flag_or 5, 4;
+    %jmp/0xz T_0.1, 5;
+    %load/vec4 v0x55b401210070_0;
+    %pad/u 32;
+    %load/vec4 v0x55b401210070_0;
+    %pad/u 7;
+    %ix/vec4 4;
+    %store/vec4a v0x55b40120fef0, 4, 0;
+    %load/vec4 v0x55b401210070_0;
+    %addi 1, 0, 6;
+    %store/vec4 v0x55b401210070_0, 0, 6;
+    %jmp T_0.0;
+T_0.1 ;
+    %pushi/vec4 4270112, 0, 32;
+    %ix/load 4, 0, 0;
+    %flag_set/imm 4, 0;
+    %store/vec4a v0x55b40120f8f0, 4, 0;
+    %pushi/vec4 32, 0, 32;
+    %ix/load 4, 1, 0;
+    %flag_set/imm 4, 0;
+    %store/vec4a v0x55b40120f8f0, 4, 0;
+    %pushi/vec4 32, 0, 32;
+    %ix/load 4, 2, 0;
+    %flag_set/imm 4, 0;
+    %store/vec4a v0x55b40120f8f0, 4, 0;
+    %pushi/vec4 32, 0, 32;
+    %ix/load 4, 3, 0;
+    %flag_set/imm 4, 0;
+    %store/vec4a v0x55b40120f8f0, 4, 0;
+    %pushi/vec4 2359492612, 0, 32;
+    %ix/load 4, 4, 0;
+    %flag_set/imm 4, 0;
+    %store/vec4a v0x55b40120f8f0, 4, 0;
+    %pushi/vec4 2353135616, 0, 32;
+    %ix/load 4, 5, 0;
+    %flag_set/imm 4, 0;
+    %store/vec4a v0x55b40120f8f0, 4, 0;
+    %pushi/vec4 32, 0, 32;
+    %ix/load 4, 6, 0;
+    %flag_set/imm 4, 0;
+    %store/vec4a v0x55b40120f8f0, 4, 0;
+    %pushi/vec4 32, 0, 32;
+    %ix/load 4, 7, 0;
+    %flag_set/imm 4, 0;
+    %store/vec4a v0x55b40120f8f0, 4, 0;
+    %pushi/vec4 10688549, 0, 32;
+    %ix/load 4, 8, 0;
+    %flag_set/imm 4, 0;
+    %store/vec4a v0x55b40120f8f0, 4, 0;
+    %pushi/vec4 32, 0, 32;
+    %ix/load 4, 9, 0;
+    %flag_set/imm 4, 0;
+    %store/vec4a v0x55b40120f8f0, 4, 0;
+    %pushi/vec4 32, 0, 32;
+    %ix/load 4, 10, 0;
+    %flag_set/imm 4, 0;
+    %store/vec4a v0x55b40120f8f0, 4, 0;
+    %pushi/vec4 32, 0, 32;
+    %ix/load 4, 11, 0;
+    %flag_set/imm 4, 0;
+    %store/vec4a v0x55b40120f8f0, 4, 0;
+    %pushi/vec4 2896363520, 0, 32;
+    %ix/load 4, 12, 0;
+    %flag_set/imm 4, 0;
+    %store/vec4a v0x55b40120f8f0, 4, 0;
+    %pushi/vec4 13, 0, 11;
+    %store/vec4 v0x55b401210150_0, 0, 11;
+T_0.2 ;
+    %load/vec4 v0x55b401210150_0;
+    %pad/u 32;
+    %cmpi/u 1023, 0, 32;
+    %flag_or 5, 4;
+    %jmp/0xz T_0.3, 5;
+    %pushi/vec4 32, 0, 32;
+    %load/vec4 v0x55b401210150_0;
+    %pad/u 12;
+    %ix/vec4 4;
+    %store/vec4a v0x55b40120f8f0, 4, 0;
+    %load/vec4 v0x55b401210150_0;
+    %addi 1, 0, 11;
+    %store/vec4 v0x55b401210150_0, 0, 11;
+    %jmp T_0.2;
+T_0.3 ;
+    %pushi/vec4 0, 0, 32;
+    %ix/load 4, 0, 0;
+    %flag_set/imm 4, 0;
+    %store/vec4a v0x55b40120ed80, 4, 0;
+    %pushi/vec4 4294967295, 0, 32;
+    %ix/load 4, 1, 0;
+    %flag_set/imm 4, 0;
+    %store/vec4a v0x55b40120ed80, 4, 0;
+    %pushi/vec4 2, 0, 11;
+    %store/vec4 v0x55b401210230_0, 0, 11;
+T_0.4 ;
+    %load/vec4 v0x55b401210230_0;
+    %pad/u 32;
+    %cmpi/u 1023, 0, 32;
+    %flag_or 5, 4;
+    %jmp/0xz T_0.5, 5;
+    %pushi/vec4 0, 0, 32;
+    %load/vec4 v0x55b401210230_0;
+    %pad/u 12;
+    %ix/vec4 4;
+    %store/vec4a v0x55b40120ed80, 4, 0;
+    %load/vec4 v0x55b401210230_0;
+    %addi 1, 0, 11;
+    %store/vec4 v0x55b401210230_0, 0, 11;
+    %jmp T_0.4;
+T_0.5 ;
+    %end;
+    .thread T_0;
+    .scope S_0x55b4011cc9a0;
+T_1 ;
+    %wait E_0x55b4011e1270;
+    %load/vec4 v0x55b40120fe10_0;
+    %ix/load 5, 2, 0;
+    %flag_set/imm 4, 0;
+    %shiftr 5;
+    %ix/vec4 4;
+    %load/vec4a v0x55b40120f8f0, 4;
+    %assign/vec4 v0x55b40120f810_0, 0;
+    %load/vec4 v0x55b40120fe10_0;
+    %addi 4, 0, 32;
+    %assign/vec4 v0x55b40120fe10_0, 0;
+    %load/vec4 v0x55b40120f810_0;
+    %parti/s 5, 21, 6;
+    %pad/u 7;
+    %ix/vec4 4;
+    %load/vec4a v0x55b40120fef0, 4;
+    %assign/vec4 v0x55b40120f2d0_0, 0;
+    %load/vec4 v0x55b40120f810_0;
+    %parti/s 5, 16, 6;
+    %pad/u 7;
+    %ix/vec4 4;
+    %load/vec4a v0x55b40120fef0, 4;
+    %assign/vec4 v0x55b40120f3b0_0, 0;
+    %load/vec4 v0x55b40120f810_0;
+    %assign/vec4 v0x55b40120f490_0, 0;
+    %load/vec4 v0x55b40120f570_0;
+    %pushi/vec4 35, 0, 6;
+    %cmp/e;
+    %flag_get/vec4 4;
+    %load/vec4 v0x55b40120f570_0;
+    %pushi/vec4 43, 0, 6;
+    %cmp/e;
+    %flag_get/vec4 4;
+    %or;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_1.0, 8;
+    %load/vec4 v0x55b40120f2d0_0;
+    %load/vec4 v0x55b40120f490_0;
+    %parti/s 1, 15, 5;
+    %replicate 16;
+    %load/vec4 v0x55b40120f490_0;
+    %parti/s 16, 0, 2;
+    %concat/vec4; draw_concat_vec4
+    %add;
+    %assign/vec4 v0x55b40120ee20_0, 0;
+    %jmp T_1.1;
+T_1.0 ;
+    %load/vec4 v0x55b40120f570_0;
+    %cmpi/e 0, 0, 6;
+    %jmp/0xz  T_1.2, 4;
+    %load/vec4 v0x55b40120f490_0;
+    %parti/s 6, 0, 2;
+    %dup/vec4;
+    %pushi/vec4 32, 0, 6;
+    %cmp/u;
+    %jmp/1 T_1.4, 6;
+    %dup/vec4;
+    %pushi/vec4 37, 0, 6;
+    %cmp/u;
+    %jmp/1 T_1.5, 6;
+    %jmp T_1.7;
+T_1.4 ;
+    %load/vec4 v0x55b4011d6de0_0;
+    %load/vec4 v0x55b40120eca0_0;
+    %add;
+    %assign/vec4 v0x55b40120ee20_0, 0;
+    %jmp T_1.7;
+T_1.5 ;
+    %load/vec4 v0x55b4011d6de0_0;
+    %load/vec4 v0x55b40120eca0_0;
+    %or;
+    %assign/vec4 v0x55b40120ee20_0, 0;
+    %jmp T_1.7;
+T_1.7 ;
+    %pop/vec4 1;
+T_1.2 ;
+T_1.1 ;
+    %load/vec4 v0x55b40120f490_0;
+    %assign/vec4 v0x55b40120f030_0, 0;
+    %load/vec4 v0x55b40120f3b0_0;
+    %assign/vec4 v0x55b40120ef00_0, 0;
+    %load/vec4 v0x55b40120f110_0;
+    %cmpi/e 0, 0, 6;
+    %jmp/0xz  T_1.8, 4;
+    %load/vec4 v0x55b40120ee20_0;
+    %assign/vec4 v0x55b40120fa90_0, 0;
+    %jmp T_1.9;
+T_1.8 ;
+    %load/vec4 v0x55b40120f110_0;
+    %cmpi/e 35, 0, 6;
+    %jmp/0xz  T_1.10, 4;
+    %load/vec4 v0x55b40120ee20_0;
+    %ix/load 5, 2, 0;
+    %flag_set/imm 4, 0;
+    %shiftr 5;
+    %ix/vec4 4;
+    %load/vec4a v0x55b40120ed80, 4;
+    %assign/vec4 v0x55b40120fa90_0, 0;
+    %jmp T_1.11;
+T_1.10 ;
+    %load/vec4 v0x55b40120f110_0;
+    %cmpi/e 43, 0, 6;
+    %jmp/0xz  T_1.12, 4;
+    %load/vec4 v0x55b40120ef00_0;
+    %load/vec4 v0x55b40120ee20_0;
+    %ix/load 4, 2, 0;
+    %flag_set/imm 4, 0;
+    %shiftr 4;
+    %ix/vec4 3;
+    %ix/load 4, 0, 0; Constant delay
+    %assign/vec4/a/d v0x55b40120ed80, 0, 4;
+T_1.12 ;
+T_1.11 ;
+T_1.9 ;
+    %load/vec4 v0x55b40120f030_0;
+    %assign/vec4 v0x55b40120f9b0_0, 0;
+    %load/vec4 v0x55b40120fb70_0;
+    %pushi/vec4 0, 0, 6;
+    %cmp/e;
+    %flag_get/vec4 4;
+    %load/vec4 v0x55b40120fc50_0;
+    %pad/u 32;
+    %pushi/vec4 0, 0, 32;
+    %cmp/e;
+    %flag_get/vec4 4;
+    %inv;
+    %and;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_1.14, 8;
+    %load/vec4 v0x55b40120fa90_0;
+    %load/vec4 v0x55b40120fc50_0;
+    %pad/u 7;
+    %ix/vec4 3;
+    %ix/load 4, 0, 0; Constant delay
+    %assign/vec4/a/d v0x55b40120fef0, 0, 4;
+    %jmp T_1.15;
+T_1.14 ;
+    %load/vec4 v0x55b40120fb70_0;
+    %pushi/vec4 35, 0, 6;
+    %cmp/e;
+    %flag_get/vec4 4;
+    %load/vec4 v0x55b40120fd30_0;
+    %pad/u 32;
+    %pushi/vec4 0, 0, 32;
+    %cmp/e;
+    %flag_get/vec4 4;
+    %inv;
+    %and;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_1.16, 8;
+    %load/vec4 v0x55b40120fa90_0;
+    %load/vec4 v0x55b40120fd30_0;
+    %pad/u 7;
+    %ix/vec4 3;
+    %ix/load 4, 0, 0; Constant delay
+    %assign/vec4/a/d v0x55b40120fef0, 0, 4;
+T_1.16 ;
+T_1.15 ;
+    %jmp T_1;
+    .thread T_1;
+    .scope S_0x55b4011cce40;
+T_2 ;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x55b401210350_0, 0, 1;
+    %pushi/vec4 0, 0, 4;
+    %store/vec4 v0x55b4012103f0_0, 0, 4;
+    %delay 160, 0;
+    %vpi_call 2 20 "$finish" {0 0 0};
+    %end;
+    .thread T_2;
+    .scope S_0x55b4011cce40;
+T_3 ;
+    %delay 5, 0;
+    %load/vec4 v0x55b401210350_0;
+    %inv;
+    %store/vec4 v0x55b401210350_0, 0, 1;
+    %jmp T_3;
+    .thread T_3;
+    .scope S_0x55b4011cce40;
+T_4 ;
+    %wait E_0x55b4011e1270;
+    %load/vec4 v0x55b4012103f0_0;
+    %addi 1, 0, 4;
+    %store/vec4 v0x55b4012103f0_0, 0, 4;
+    %jmp T_4;
+    .thread T_4;
+    .scope S_0x55b4011cce40;
+T_5 ;
+    %wait E_0x55b4011e0f80;
+    %vpi_call 2 36 "$display", "\012\012clock cycle = %d", v0x55b4012103f0_0, " (time = %1.0t)", $time {0 0 0};
+    %vpi_call 2 37 "$display", "IF/ID registers\012\011 IF/ID.PC+4 = %h, IF/ID.IR = %h \012", v0x55b40120fe10_0, v0x55b40120f810_0 {0 0 0};
+    %vpi_call 2 38 "$display", "ID/EX registers\012\011 ID/EX.rs = %d, ID/EX.rt = %d", v0x55b40120f650_0, v0x55b40120f730_0, "\012\011 ID/EX.A = %h, ID/EX.B = %h", v0x55b40120f2d0_0, v0x55b40120f3b0_0 {0 0 0};
+    %vpi_call 2 39 "$display", "\011 ID/EX.op = %h\012", v0x55b40120f570_0 {0 0 0};
+    %vpi_call 2 40 "$display", "EX/MEM registers\012\011 EX/MEM.rs = %d, EX/MEM.rt = %d", v0x55b40120f650_0, v0x55b40120f730_0, "\012\011 EX/MEM.ALUOut = %h, EX/MEM.ALUout = %h", v0x55b40120ee20_0, v0x55b40120ef00_0 {0 0 0};
+    %vpi_call 2 41 "$display", "\011 EX/MEM.op = %h\012", v0x55b40120f110_0 {0 0 0};
+    %vpi_call 2 42 "$display", "MEM/WB registers\012\011 MEM/WB.rd = %d, MEM/WB.rt = %d", v0x55b40120fc50_0, v0x55b40120fd30_0, "\012\011 MEM/WB.value = %h", v0x55b40120fa90_0 {0 0 0};
+    %vpi_call 2 43 "$display", "\011 EX/MEM.op = %h\012", v0x55b40120fb70_0 {0 0 0};
+    %jmp T_5;
+    .thread T_5;
+    .scope S_0x55b4011cce40;
+T_6 ;
+    %vpi_call 2 49 "$dumpfile", "test_mipspipe.vcd" {0 0 0};
+    %vpi_call 2 50 "$dumpvars" {0 0 0};
+    %end;
+    .thread T_6;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+    "N/A";
+    "<interactive>";
+    "test_mipspipe.v";
+    "./mipspipe.v";
diff --git a/OLD/ee4363/mp1/mp12/test_mipspipe.v b/OLD/ee4363/mp1/mp12/test_mipspipe.v
new file mode 100644
index 0000000..24576ec
--- /dev/null
+++ b/OLD/ee4363/mp1/mp12/test_mipspipe.v
@@ -0,0 +1,53 @@
+//
+// Test bench for the mipspipe
+// Boram Lee
+//
+  
+`include "mipspipe.v"
+  
+module test_mipspipe;
+  
+  reg clock;
+  reg [3:0] clock_cycle;
+
+// instantiate pipeline module
+  mipspipe u_mipspipe(clock);
+ 
+// initialize clock and cycle counter 
+  initial begin
+    clock = 0;
+    clock_cycle=4'h0;
+    #160  $finish;
+  end
+  
+// 10 unit clock cycle
+  always 
+    #5 clock = ~clock;
+
+  always @(posedge clock)
+     begin
+       clock_cycle=clock_cycle+1;
+     end
+
+
+// display contents of pipeline latches at the end of each clock cycle
+  always @(negedge clock) 
+     begin
+     $display("\n\nclock cycle = %d",clock_cycle," (time = %1.0t)",$time);
+     $display("IF/ID registers\n\t IF/ID.PC+4 = %h, IF/ID.IR = %h \n", u_mipspipe.PC, u_mipspipe.IFIDIR); 
+     $display("ID/EX registers\n\t ID/EX.rs = %d, ID/EX.rt = %d",u_mipspipe.IDEXrs,u_mipspipe.IDEXrt,"\n\t ID/EX.A = %h, ID/EX.B = %h",u_mipspipe.IDEXA,u_mipspipe.IDEXB);
+     $display("\t ID/EX.op = %h\n",u_mipspipe.IDEXop);
+     $display("EX/MEM registers\n\t EX/MEM.rs = %d, EX/MEM.rt = %d",u_mipspipe.IDEXrs,u_mipspipe.IDEXrt,"\n\t EX/MEM.ALUOut = %h, EX/MEM.ALUout = %h",u_mipspipe.EXMEMALUOut,u_mipspipe.EXMEMB);
+     $display("\t EX/MEM.op = %h\n",u_mipspipe.EXMEMop);
+     $display("MEM/WB registers\n\t MEM/WB.rd = %d, MEM/WB.rt = %d",u_mipspipe.MEMWBrd,u_mipspipe.MEMWBrt,"\n\t MEM/WB.value = %h",u_mipspipe.MEMWBValue);
+     $display("\t EX/MEM.op = %h\n",u_mipspipe.MEMWBop);
+     end
+      
+// log to a vcd (variable change dump) file
+   initial
+      begin
+      $dumpfile("test_mipspipe.vcd");
+      $dumpvars;
+   end
+
+endmodule
diff --git a/OLD/ee4363/mp1/mp12/test_mipspipe.vcd b/OLD/ee4363/mp1/mp12/test_mipspipe.vcd
new file mode 100644
index 0000000..d70b8fd
--- /dev/null
+++ b/OLD/ee4363/mp1/mp12/test_mipspipe.vcd
@@ -0,0 +1,311 @@
+$date
+	Thu Dec  3 19:41:59 2020
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module test_mipspipe $end
+$var reg 1 ! clock $end
+$var reg 4 " clock_cycle [3:0] $end
+$scope module u_mipspipe $end
+$var wire 32 # Ain [31:0] $end
+$var wire 32 $ Bin [31:0] $end
+$var wire 1 ! clock $end
+$var wire 5 % MEMWBrt [4:0] $end
+$var wire 5 & MEMWBrd [4:0] $end
+$var wire 6 ' MEMWBop [5:0] $end
+$var wire 5 ( IDEXrt [4:0] $end
+$var wire 5 ) IDEXrs [4:0] $end
+$var wire 6 * IDEXop [5:0] $end
+$var wire 5 + EXMEMrd [4:0] $end
+$var wire 6 , EXMEMop [5:0] $end
+$var reg 32 - EXMEMALUOut [31:0] $end
+$var reg 32 . EXMEMB [31:0] $end
+$var reg 32 / EXMEMIR [31:0] $end
+$var reg 32 0 IDEXA [31:0] $end
+$var reg 32 1 IDEXB [31:0] $end
+$var reg 32 2 IDEXIR [31:0] $end
+$var reg 32 3 IFIDIR [31:0] $end
+$var reg 32 4 MEMWBIR [31:0] $end
+$var reg 32 5 MEMWBValue [31:0] $end
+$var reg 32 6 PC [31:0] $end
+$var reg 6 7 i [5:0] $end
+$var reg 11 8 j [10:0] $end
+$var reg 11 9 k [10:0] $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+b10000000000 9
+b10000000000 8
+b100000 7
+b0 6
+bx 5
+b100000 4
+b100000 3
+b100000 2
+bx 1
+bx 0
+b100000 /
+bx .
+bx -
+b0 ,
+b0 +
+b0 *
+b0 )
+b0 (
+b0 '
+b0 &
+b0 %
+bx $
+bx #
+b0 "
+0!
+$end
+#5
+b0 $
+b0 1
+b0 #
+b0 0
+b100 6
+b10000010010100000100000 3
+b1 "
+1!
+#10
+0!
+#15
+b10 )
+b1 (
+b0 .
+b0 -
+b10000010010100000100000 2
+b1 $
+b1 1
+b10 #
+b10 0
+b1000 6
+b100000 3
+b10 "
+1!
+#20
+0!
+#25
+b101 +
+b0 )
+b0 (
+b0 5
+b1 .
+b10000010010100000100000 /
+b11 -
+b100000 2
+b0 $
+b0 1
+b0 #
+b0 0
+b1100 6
+b11 "
+1!
+#30
+0!
+#35
+b101 &
+b1 %
+b0 +
+b10000010010100000100000 4
+b11 5
+b0 .
+b100000 /
+b0 -
+b10000 6
+b100 "
+1!
+#40
+0!
+#45
+b0 &
+b0 %
+b100000 4
+b0 5
+b10100 6
+b10001100101000110000000000000100 3
+b101 "
+1!
+#50
+0!
+#55
+b101 )
+b11 (
+b100011 *
+b10001100101000110000000000000100 2
+b11 $
+b11 1
+b11 #
+b11 0
+b11000 6
+b10001100010000100000000000000000 3
+b110 "
+1!
+#60
+0!
+#65
+b100011 ,
+b10 )
+b10 (
+b11 .
+b10001100101000110000000000000100 /
+b111 -
+b10001100010000100000000000000000 2
+b10 $
+b10 1
+b10 #
+b10 0
+b11100 6
+b100000 3
+b111 "
+1!
+#70
+0!
+#75
+b11 %
+b100011 '
+b0 )
+b0 (
+b0 *
+b10001100101000110000000000000100 4
+b11111111111111111111111111111111 5
+b10 .
+b10001100010000100000000000000000 /
+b10 -
+b100000 2
+b0 $
+b0 1
+b0 #
+b0 0
+b100000 6
+b1000 "
+1!
+#80
+0!
+#85
+b10 %
+b0 ,
+b10001100010000100000000000000000 4
+b0 5
+b0 .
+b100000 /
+b0 -
+b100100 6
+b101000110001100000100101 3
+b1001 "
+1!
+#90
+0!
+#95
+b0 %
+b0 '
+b101 )
+b11 (
+b100000 4
+b101000110001100000100101 2
+b11111111111111111111111111111111 $
+b11111111111111111111111111111111 1
+b11 #
+b11 0
+b101000 6
+b100000 3
+b1010 "
+1!
+#100
+0!
+#105
+b11 +
+b0 )
+b0 (
+b11111111111111111111111111111111 .
+b101000110001100000100101 /
+b11111111111111111111111111111111 -
+b100000 2
+b0 $
+b0 1
+b0 #
+b0 0
+b101100 6
+b1011 "
+1!
+#110
+0!
+#115
+b11 &
+b11 %
+b0 +
+b101000110001100000100101 4
+b11111111111111111111111111111111 5
+b0 .
+b100000 /
+b0 -
+b110000 6
+b1100 "
+1!
+#120
+0!
+#125
+b0 &
+b0 %
+b100000 4
+b0 5
+b110100 6
+b10101100101000110000000000000000 3
+b1101 "
+1!
+#130
+0!
+#135
+b101 )
+b11 (
+b101011 *
+b10101100101000110000000000000000 2
+b11111111111111111111111111111111 $
+b11111111111111111111111111111111 1
+b11 #
+b11 0
+b111000 6
+b100000 3
+b1110 "
+1!
+#140
+0!
+#145
+b101011 ,
+b0 )
+b0 (
+b0 *
+b11111111111111111111111111111111 .
+b10101100101000110000000000000000 /
+b11 -
+b100000 2
+b0 $
+b0 1
+b0 #
+b0 0
+b111100 6
+b1111 "
+1!
+#150
+0!
+#155
+b11 %
+b101011 '
+b0 ,
+b10101100101000110000000000000000 4
+b0 .
+b100000 /
+b0 -
+b1000000 6
+b0 "
+1!
+#160
+0!