aaaaaaaaaaaaa

2 files changed, 813 insertions, 0 deletions

diff --git a/ee4363/mp2/out b/ee4363/mp2/out
new file mode 100644
index 0000000..21917ca
--- /dev/null
+++ b/ee4363/mp2/out
@@ -0,0 +1,441 @@
+#! /usr/bin/vvp
+:ivl_version "10.3 (stable)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "system";
+:vpi_module "vhdl_sys";
+:vpi_module "v2005_math";
+:vpi_module "va_math";
+S_0x557ce3145980 .scope module, "test_mipspipe" "test_mipspipe" 2 8;
+ .timescale 0 0;
+v0x557ce3191970_0 .var "clock", 0 0;
+v0x557ce3191a10_0 .var "clock_cycle", 3 0;
+E_0x557ce315b100 .event negedge, v0x557ce31915d0_0;
+S_0x557ce314d3e0 .scope module, "u_mipspipe_mp2" "mipspipe_mp2" 2 14, 3 3 0, S_0x557ce3145980;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "clock"
+P_0x557ce314c090 .param/l "ALUop" 0 3 8, C4<000000>;
+P_0x557ce314c0d0 .param/l "BEQ" 0 3 8, C4<000100>;
+P_0x557ce314c110 .param/l "LW" 0 3 8, C4<100011>;
+P_0x557ce314c150 .param/l "SW" 0 3 8, C4<101011>;
+P_0x557ce314c190 .param/l "nop" 0 3 8, C4<00000000000000000000000000100000>;
+L_0x557ce31544c0 .functor AND 1, L_0x557ce31921f0, L_0x557ce31a24a0, C4<1>, C4<1>;
+L_0x557ce311fa40 .functor AND 1, L_0x557ce31544c0, L_0x557ce31a26b0, C4<1>, C4<1>;
+L_0x557ce31a27f0 .functor AND 1, L_0x557ce31a29f0, L_0x557ce31a2c10, C4<1>, C4<1>;
+L_0x557ce311f820 .functor AND 1, L_0x557ce31a27f0, L_0x557ce31a2f40, C4<1>, C4<1>;
+L_0x7f83ba241138 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+L_0x557ce311f930 .functor OR 1, L_0x7f83ba241138, L_0x557ce311f820, C4<0>, C4<0>;
+L_0x557ce31543f0 .functor BUFZ 32, v0x557ce318f570_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+v0x557ce316a9a0_0 .net "Ain", 31 0, L_0x557ce31a3330;  1 drivers
+v0x557ce318ee60_0 .net "Bin", 31 0, L_0x557ce31543f0;  1 drivers
+v0x557ce318ef40 .array "DMemory", 1023 0, 31 0;
+v0x557ce318efe0_0 .var "EXMEMALUOut", 31 0;
+v0x557ce318f0c0_0 .var "EXMEMB", 31 0;
+v0x557ce318f1f0_0 .var "EXMEMIR", 31 0;
+v0x557ce318f2d0_0 .net "EXMEMop", 5 0, L_0x557ce3191f30;  1 drivers
+v0x557ce318f3b0_0 .net "EXMEMrd", 4 0, L_0x557ce3191c10;  1 drivers
+v0x557ce318f490_0 .var "IDEXA", 31 0;
+v0x557ce318f570_0 .var "IDEXB", 31 0;
+v0x557ce318f650_0 .var "IDEXIR", 31 0;
+v0x557ce318f730_0 .net "IDEXop", 5 0, L_0x557ce3192100;  1 drivers
+v0x557ce318f810_0 .net "IDEXrs", 4 0, L_0x557ce3191ad0;  1 drivers
+v0x557ce318f8f0_0 .net "IDEXrt", 4 0, L_0x557ce3191b70;  1 drivers
+v0x557ce318f9d0_0 .var "IFIDIR", 31 0;
+v0x557ce318fab0 .array "IMemory", 1023 0, 31 0;
+v0x557ce318fb70_0 .var "MEMWBIR", 31 0;
+v0x557ce318fc50_0 .var "MEMWBValue", 31 0;
+v0x557ce318fd30_0 .net "MEMWBop", 5 0, L_0x557ce3192060;  1 drivers
+v0x557ce318fe10_0 .net "MEMWBrd", 4 0, L_0x557ce3191ce0;  1 drivers
+v0x557ce318fef0_0 .net "MEMWBrt", 4 0, L_0x557ce3191e10;  1 drivers
+v0x557ce318ffd0_0 .var "PC", 31 0;
+v0x557ce31900b0 .array "Regs", 31 0, 31 0;
+v0x557ce3190170_0 .net *"_s16", 0 0, L_0x557ce31921f0;  1 drivers
+v0x557ce3190230_0 .net *"_s18", 31 0, L_0x557ce3192360;  1 drivers
+L_0x7f83ba241018 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0x557ce3190310_0 .net *"_s21", 26 0, L_0x7f83ba241018;  1 drivers
+L_0x7f83ba241060 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0x557ce31903f0_0 .net/2u *"_s22", 31 0, L_0x7f83ba241060;  1 drivers
+v0x557ce31904d0_0 .net *"_s24", 0 0, L_0x557ce31a24a0;  1 drivers
+v0x557ce3190590_0 .net *"_s26", 0 0, L_0x557ce31544c0;  1 drivers
+L_0x7f83ba2410a8 .functor BUFT 1, C4<000000>, C4<0>, C4<0>, C4<0>;
+v0x557ce3190670_0 .net/2u *"_s28", 5 0, L_0x7f83ba2410a8;  1 drivers
+v0x557ce3190750_0 .net *"_s30", 0 0, L_0x557ce31a26b0;  1 drivers
+v0x557ce3190810_0 .net *"_s41", 4 0, L_0x557ce31a2950;  1 drivers
+v0x557ce31908f0_0 .net *"_s42", 0 0, L_0x557ce31a29f0;  1 drivers
+v0x557ce31909b0_0 .net *"_s44", 31 0, L_0x557ce31a2b40;  1 drivers
+L_0x7f83ba2411c8 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0x557ce3190a90_0 .net *"_s47", 26 0, L_0x7f83ba2411c8;  1 drivers
+L_0x7f83ba241210 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0x557ce3190b70_0 .net/2u *"_s48", 31 0, L_0x7f83ba241210;  1 drivers
+v0x557ce3190c50_0 .net *"_s50", 0 0, L_0x557ce31a2c10;  1 drivers
+v0x557ce3190d10_0 .net *"_s52", 0 0, L_0x557ce31a27f0;  1 drivers
+L_0x7f83ba241258 .functor BUFT 1, C4<100011>, C4<0>, C4<0>, C4<0>;
+v0x557ce3190df0_0 .net/2u *"_s54", 5 0, L_0x7f83ba241258;  1 drivers
+v0x557ce3190ed0_0 .net *"_s56", 0 0, L_0x557ce31a2f40;  1 drivers
+v0x557ce3190f90_0 .net *"_s62", 0 0, L_0x557ce311f930;  1 drivers
+v0x557ce3191070_0 .net *"_s64", 31 0, L_0x557ce31a31a0;  1 drivers
+v0x557ce3191150_0 .net "bypassAfromALUinWB", 0 0, L_0x7f83ba241138;  1 drivers
+v0x557ce3191210_0 .net "bypassAfromLWinWB", 0 0, L_0x557ce311f820;  1 drivers
+v0x557ce31912d0_0 .net "bypassAfromMEM", 0 0, L_0x557ce311fa40;  1 drivers
+L_0x7f83ba241180 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0x557ce3191390_0 .net "bypassBfromALUinWB", 0 0, L_0x7f83ba241180;  1 drivers
+L_0x7f83ba2412a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0x557ce3191450_0 .net "bypassBfromLWinWB", 0 0, L_0x7f83ba2412a0;  1 drivers
+L_0x7f83ba2410f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0x557ce3191510_0 .net "bypassBfromMEM", 0 0, L_0x7f83ba2410f0;  1 drivers
+v0x557ce31915d0_0 .net "clock", 0 0, v0x557ce3191970_0;  1 drivers
+v0x557ce3191690_0 .var "i", 5 0;
+v0x557ce3191770_0 .var "j", 10 0;
+v0x557ce3191850_0 .var "k", 10 0;
+E_0x557ce315b3f0 .event posedge, v0x557ce31915d0_0;
+L_0x557ce3191ad0 .part v0x557ce318f650_0, 21, 5;
+L_0x557ce3191b70 .part v0x557ce318f650_0, 16, 5;
+L_0x557ce3191c10 .part v0x557ce318f1f0_0, 11, 5;
+L_0x557ce3191ce0 .part v0x557ce318fb70_0, 11, 5;
+L_0x557ce3191e10 .part v0x557ce318fb70_0, 16, 5;
+L_0x557ce3191f30 .part v0x557ce318f1f0_0, 26, 6;
+L_0x557ce3192060 .part v0x557ce318fb70_0, 26, 6;
+L_0x557ce3192100 .part v0x557ce318f650_0, 26, 6;
+L_0x557ce31921f0 .cmp/eq 5, L_0x557ce3191ad0, L_0x557ce3191c10;
+L_0x557ce3192360 .concat [ 5 27 0 0], L_0x557ce3191ad0, L_0x7f83ba241018;
+L_0x557ce31a24a0 .cmp/ne 32, L_0x557ce3192360, L_0x7f83ba241060;
+L_0x557ce31a26b0 .cmp/eq 6, L_0x557ce3191f30, L_0x7f83ba2410a8;
+L_0x557ce31a2950 .part v0x557ce318fb70_0, 16, 5;
+L_0x557ce31a29f0 .cmp/eq 5, L_0x557ce3191ad0, L_0x557ce31a2950;
+L_0x557ce31a2b40 .concat [ 5 27 0 0], L_0x557ce3191ad0, L_0x7f83ba2411c8;
+L_0x557ce31a2c10 .cmp/ne 32, L_0x557ce31a2b40, L_0x7f83ba241210;
+L_0x557ce31a2f40 .cmp/eq 6, L_0x557ce3192060, L_0x7f83ba241258;
+L_0x557ce31a31a0 .functor MUXZ 32, v0x557ce318f490_0, v0x557ce318fc50_0, L_0x557ce311f930, C4<>;
+L_0x557ce31a3330 .functor MUXZ 32, L_0x557ce31a31a0, v0x557ce318efe0_0, L_0x557ce311fa40, C4<>;
+    .scope S_0x557ce314d3e0;
+T_0 ;
+    %pushi/vec4 0, 0, 32;
+    %store/vec4 v0x557ce318ffd0_0, 0, 32;
+    %pushi/vec4 32, 0, 32;
+    %store/vec4 v0x557ce318f9d0_0, 0, 32;
+    %pushi/vec4 32, 0, 32;
+    %store/vec4 v0x557ce318f650_0, 0, 32;
+    %pushi/vec4 32, 0, 32;
+    %store/vec4 v0x557ce318f1f0_0, 0, 32;
+    %pushi/vec4 32, 0, 32;
+    %store/vec4 v0x557ce318fb70_0, 0, 32;
+    %pushi/vec4 0, 0, 6;
+    %store/vec4 v0x557ce3191690_0, 0, 6;
+T_0.0 ;
+    %load/vec4 v0x557ce3191690_0;
+    %pad/u 32;
+    %cmpi/u 31, 0, 32;
+    %flag_or 5, 4;
+    %jmp/0xz T_0.1, 5;
+    %load/vec4 v0x557ce3191690_0;
+    %pad/u 32;
+    %load/vec4 v0x557ce3191690_0;
+    %pad/u 7;
+    %ix/vec4 4;
+    %store/vec4a v0x557ce31900b0, 4, 0;
+    %load/vec4 v0x557ce3191690_0;
+    %addi 1, 0, 6;
+    %store/vec4 v0x557ce3191690_0, 0, 6;
+    %jmp T_0.0;
+T_0.1 ;
+    %pushi/vec4 4270112, 0, 32;
+    %ix/load 4, 0, 0;
+    %flag_set/imm 4, 0;
+    %store/vec4a v0x557ce318fab0, 4, 0;
+    %pushi/vec4 2359492612, 0, 32;
+    %ix/load 4, 1, 0;
+    %flag_set/imm 4, 0;
+    %store/vec4a v0x557ce318fab0, 4, 0;
+    %pushi/vec4 2896625669, 0, 32;
+    %ix/load 4, 2, 0;
+    %flag_set/imm 4, 0;
+    %store/vec4a v0x557ce318fab0, 4, 0;
+    %pushi/vec4 6299680, 0, 32;
+    %ix/load 4, 3, 0;
+    %flag_set/imm 4, 0;
+    %store/vec4a v0x557ce318fab0, 4, 0;
+    %pushi/vec4 17379360, 0, 32;
+    %ix/load 4, 4, 0;
+    %flag_set/imm 4, 0;
+    %store/vec4a v0x557ce318fab0, 4, 0;
+    %pushi/vec4 2886074380, 0, 32;
+    %ix/load 4, 5, 0;
+    %flag_set/imm 4, 0;
+    %store/vec4a v0x557ce318fab0, 4, 0;
+    %pushi/vec4 12603424, 0, 32;
+    %ix/load 4, 6, 0;
+    %flag_set/imm 4, 0;
+    %store/vec4a v0x557ce318fab0, 4, 0;
+    %pushi/vec4 2349531152, 0, 32;
+    %ix/load 4, 7, 0;
+    %flag_set/imm 4, 0;
+    %store/vec4a v0x557ce318fab0, 4, 0;
+    %pushi/vec4 32, 0, 32;
+    %ix/load 4, 8, 0;
+    %flag_set/imm 4, 0;
+    %store/vec4a v0x557ce318fab0, 4, 0;
+    %pushi/vec4 2842656, 0, 32;
+    %ix/load 4, 9, 0;
+    %flag_set/imm 4, 0;
+    %store/vec4a v0x557ce318fab0, 4, 0;
+    %pushi/vec4 10, 0, 11;
+    %store/vec4 v0x557ce3191770_0, 0, 11;
+T_0.2 ;
+    %load/vec4 v0x557ce3191770_0;
+    %pad/u 32;
+    %cmpi/u 1023, 0, 32;
+    %flag_or 5, 4;
+    %jmp/0xz T_0.3, 5;
+    %pushi/vec4 32, 0, 32;
+    %load/vec4 v0x557ce3191770_0;
+    %pad/u 12;
+    %ix/vec4 4;
+    %store/vec4a v0x557ce318fab0, 4, 0;
+    %load/vec4 v0x557ce3191770_0;
+    %addi 1, 0, 11;
+    %store/vec4 v0x557ce3191770_0, 0, 11;
+    %jmp T_0.2;
+T_0.3 ;
+    %pushi/vec4 0, 0, 32;
+    %ix/load 4, 0, 0;
+    %flag_set/imm 4, 0;
+    %store/vec4a v0x557ce318ef40, 4, 0;
+    %pushi/vec4 4294967295, 0, 32;
+    %ix/load 4, 1, 0;
+    %flag_set/imm 4, 0;
+    %store/vec4a v0x557ce318ef40, 4, 0;
+    %pushi/vec4 0, 0, 32;
+    %ix/load 4, 2, 0;
+    %flag_set/imm 4, 0;
+    %store/vec4a v0x557ce318ef40, 4, 0;
+    %pushi/vec4 0, 0, 32;
+    %ix/load 4, 3, 0;
+    %flag_set/imm 4, 0;
+    %store/vec4a v0x557ce318ef40, 4, 0;
+    %pushi/vec4 4294967294, 0, 32;
+    %ix/load 4, 4, 0;
+    %flag_set/imm 4, 0;
+    %store/vec4a v0x557ce318ef40, 4, 0;
+    %pushi/vec4 5, 0, 11;
+    %store/vec4 v0x557ce3191850_0, 0, 11;
+T_0.4 ;
+    %load/vec4 v0x557ce3191850_0;
+    %pad/u 32;
+    %cmpi/u 1023, 0, 32;
+    %flag_or 5, 4;
+    %jmp/0xz T_0.5, 5;
+    %pushi/vec4 0, 0, 32;
+    %load/vec4 v0x557ce3191850_0;
+    %pad/u 12;
+    %ix/vec4 4;
+    %store/vec4a v0x557ce318ef40, 4, 0;
+    %load/vec4 v0x557ce3191850_0;
+    %addi 1, 0, 11;
+    %store/vec4 v0x557ce3191850_0, 0, 11;
+    %jmp T_0.4;
+T_0.5 ;
+    %end;
+    .thread T_0;
+    .scope S_0x557ce314d3e0;
+T_1 ;
+    %wait E_0x557ce315b3f0;
+    %load/vec4 v0x557ce318ffd0_0;
+    %ix/load 5, 2, 0;
+    %flag_set/imm 4, 0;
+    %shiftr 5;
+    %ix/vec4 4;
+    %load/vec4a v0x557ce318fab0, 4;
+    %assign/vec4 v0x557ce318f9d0_0, 0;
+    %load/vec4 v0x557ce318ffd0_0;
+    %addi 4, 0, 32;
+    %assign/vec4 v0x557ce318ffd0_0, 0;
+    %load/vec4 v0x557ce318f9d0_0;
+    %parti/s 5, 21, 6;
+    %pad/u 7;
+    %ix/vec4 4;
+    %load/vec4a v0x557ce31900b0, 4;
+    %assign/vec4 v0x557ce318f490_0, 0;
+    %load/vec4 v0x557ce318f9d0_0;
+    %parti/s 5, 16, 6;
+    %pad/u 7;
+    %ix/vec4 4;
+    %load/vec4a v0x557ce31900b0, 4;
+    %assign/vec4 v0x557ce318f570_0, 0;
+    %load/vec4 v0x557ce318f9d0_0;
+    %assign/vec4 v0x557ce318f650_0, 0;
+    %load/vec4 v0x557ce318f730_0;
+    %pushi/vec4 35, 0, 6;
+    %cmp/e;
+    %flag_get/vec4 4;
+    %load/vec4 v0x557ce318f730_0;
+    %pushi/vec4 43, 0, 6;
+    %cmp/e;
+    %flag_get/vec4 4;
+    %or;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_1.0, 8;
+    %load/vec4 v0x557ce316a9a0_0;
+    %load/vec4 v0x557ce318f650_0;
+    %parti/s 1, 15, 5;
+    %replicate 16;
+    %load/vec4 v0x557ce318f650_0;
+    %parti/s 16, 0, 2;
+    %concat/vec4; draw_concat_vec4
+    %add;
+    %assign/vec4 v0x557ce318efe0_0, 0;
+    %jmp T_1.1;
+T_1.0 ;
+    %load/vec4 v0x557ce318f730_0;
+    %cmpi/e 0, 0, 6;
+    %jmp/0xz  T_1.2, 4;
+    %load/vec4 v0x557ce318f650_0;
+    %parti/s 6, 0, 2;
+    %dup/vec4;
+    %pushi/vec4 32, 0, 6;
+    %cmp/u;
+    %jmp/1 T_1.4, 6;
+    %jmp T_1.6;
+T_1.4 ;
+    %load/vec4 v0x557ce316a9a0_0;
+    %load/vec4 v0x557ce318ee60_0;
+    %add;
+    %assign/vec4 v0x557ce318efe0_0, 0;
+    %jmp T_1.6;
+T_1.6 ;
+    %pop/vec4 1;
+T_1.2 ;
+T_1.1 ;
+    %load/vec4 v0x557ce318f650_0;
+    %assign/vec4 v0x557ce318f1f0_0, 0;
+    %load/vec4 v0x557ce318ee60_0;
+    %assign/vec4 v0x557ce318f0c0_0, 0;
+    %load/vec4 v0x557ce318f2d0_0;
+    %cmpi/e 0, 0, 6;
+    %jmp/0xz  T_1.7, 4;
+    %load/vec4 v0x557ce318efe0_0;
+    %assign/vec4 v0x557ce318fc50_0, 0;
+    %jmp T_1.8;
+T_1.7 ;
+    %load/vec4 v0x557ce318f2d0_0;
+    %cmpi/e 35, 0, 6;
+    %jmp/0xz  T_1.9, 4;
+    %load/vec4 v0x557ce318efe0_0;
+    %ix/load 5, 2, 0;
+    %flag_set/imm 4, 0;
+    %shiftr 5;
+    %ix/vec4 4;
+    %load/vec4a v0x557ce318ef40, 4;
+    %assign/vec4 v0x557ce318fc50_0, 0;
+    %jmp T_1.10;
+T_1.9 ;
+    %load/vec4 v0x557ce318f2d0_0;
+    %cmpi/e 43, 0, 6;
+    %jmp/0xz  T_1.11, 4;
+    %load/vec4 v0x557ce318f0c0_0;
+    %load/vec4 v0x557ce318efe0_0;
+    %ix/load 4, 2, 0;
+    %flag_set/imm 4, 0;
+    %shiftr 4;
+    %ix/vec4 3;
+    %ix/load 4, 0, 0; Constant delay
+    %assign/vec4/a/d v0x557ce318ef40, 0, 4;
+T_1.11 ;
+T_1.10 ;
+T_1.8 ;
+    %load/vec4 v0x557ce318f1f0_0;
+    %assign/vec4 v0x557ce318fb70_0, 0;
+    %load/vec4 v0x557ce318fd30_0;
+    %pushi/vec4 0, 0, 6;
+    %cmp/e;
+    %flag_get/vec4 4;
+    %load/vec4 v0x557ce318fe10_0;
+    %pad/u 32;
+    %pushi/vec4 0, 0, 32;
+    %cmp/e;
+    %flag_get/vec4 4;
+    %inv;
+    %and;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_1.13, 8;
+    %load/vec4 v0x557ce318fc50_0;
+    %load/vec4 v0x557ce318fe10_0;
+    %pad/u 7;
+    %ix/vec4 3;
+    %ix/load 4, 0, 0; Constant delay
+    %assign/vec4/a/d v0x557ce31900b0, 0, 4;
+    %jmp T_1.14;
+T_1.13 ;
+    %load/vec4 v0x557ce318fd30_0;
+    %pushi/vec4 35, 0, 6;
+    %cmp/e;
+    %flag_get/vec4 4;
+    %load/vec4 v0x557ce318fef0_0;
+    %pad/u 32;
+    %pushi/vec4 0, 0, 32;
+    %cmp/e;
+    %flag_get/vec4 4;
+    %inv;
+    %and;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_1.15, 8;
+    %load/vec4 v0x557ce318fc50_0;
+    %load/vec4 v0x557ce318fef0_0;
+    %pad/u 7;
+    %ix/vec4 3;
+    %ix/load 4, 0, 0; Constant delay
+    %assign/vec4/a/d v0x557ce31900b0, 0, 4;
+T_1.15 ;
+T_1.14 ;
+    %jmp T_1;
+    .thread T_1;
+    .scope S_0x557ce3145980;
+T_2 ;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x557ce3191970_0, 0, 1;
+    %pushi/vec4 0, 0, 4;
+    %store/vec4 v0x557ce3191a10_0, 0, 4;
+    %delay 160, 0;
+    %vpi_call 2 20 "$finish" {0 0 0};
+    %end;
+    .thread T_2;
+    .scope S_0x557ce3145980;
+T_3 ;
+    %delay 5, 0;
+    %load/vec4 v0x557ce3191970_0;
+    %inv;
+    %store/vec4 v0x557ce3191970_0, 0, 1;
+    %jmp T_3;
+    .thread T_3;
+    .scope S_0x557ce3145980;
+T_4 ;
+    %wait E_0x557ce315b3f0;
+    %load/vec4 v0x557ce3191a10_0;
+    %addi 1, 0, 4;
+    %store/vec4 v0x557ce3191a10_0, 0, 4;
+    %jmp T_4;
+    .thread T_4;
+    .scope S_0x557ce3145980;
+T_5 ;
+    %wait E_0x557ce315b100;
+    %vpi_call 2 36 "$display", "\012\012clock cycle = %d", v0x557ce3191a10_0, " (time = %1.0t)", $time {0 0 0};
+    %vpi_call 2 37 "$display", "IF/ID registers\012\011 IF/ID.PC+4 = %h, IF/ID.IR = %h \012", v0x557ce318ffd0_0, v0x557ce318f9d0_0 {0 0 0};
+    %vpi_call 2 38 "$display", "ID/EX registers\012\011 ID/EX.rs = %d, ID/EX.rt = %d", v0x557ce318f810_0, v0x557ce318f8f0_0, "\012\011 ID/EX.A = %h, ID/EX.B = %h", v0x557ce318f490_0, v0x557ce318f570_0 {0 0 0};
+    %vpi_call 2 39 "$display", "\011 ID/EX.op = %h\012", v0x557ce318f730_0 {0 0 0};
+    %vpi_call 2 40 "$display", "EX/MEM registers\012\011 EX/MEM.rs = %d, EX/MEM.rt = %d", v0x557ce318f810_0, v0x557ce318f8f0_0, "\012\011 EX/MEM.ALUOut = %h, EX/MEM.ALUout = %h", v0x557ce318efe0_0, v0x557ce318f0c0_0 {0 0 0};
+    %vpi_call 2 41 "$display", "\011 EX/MEM.op = %h\012", v0x557ce318f2d0_0 {0 0 0};
+    %vpi_call 2 42 "$display", "MEM/WB registers\012\011 MEM/WB.rd = %d, MEM/WB.rt = %d", v0x557ce318fe10_0, v0x557ce318fef0_0, "\012\011 MEM/WB.value = %h", v0x557ce318fc50_0 {0 0 0};
+    %vpi_call 2 43 "$display", "\011 EX/MEM.op = %h\012", v0x557ce318fd30_0 {0 0 0};
+    %jmp T_5;
+    .thread T_5;
+    .scope S_0x557ce3145980;
+T_6 ;
+    %vpi_call 2 49 "$dumpfile", "test_mipspipe.vcd" {0 0 0};
+    %vpi_call 2 50 "$dumpvars" {0 0 0};
+    %end;
+    .thread T_6;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+    "N/A";
+    "<interactive>";
+    "test_mipspipe_mp2.v";
+    "./mipspipe_mp2.v";
diff --git a/ee4363/mp2/test_mipspipe.vcd b/ee4363/mp2/test_mipspipe.vcd
new file mode 100644
index 0000000..b75650b
--- /dev/null
+++ b/ee4363/mp2/test_mipspipe.vcd
@@ -0,0 +1,372 @@
+$date
+	Thu Dec 17 11:20:12 2020
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module test_mipspipe $end
+$var reg 1 ! clock $end
+$var reg 4 " clock_cycle [3:0] $end
+$scope module u_mipspipe_mp2 $end
+$var wire 32 # Bin [31:0] $end
+$var wire 1 $ bypassAfromALUinWB $end
+$var wire 1 % bypassAfromLWinWB $end
+$var wire 1 & bypassAfromMEM $end
+$var wire 1 ' bypassBfromALUinWB $end
+$var wire 1 ( bypassBfromLWinWB $end
+$var wire 1 ) bypassBfromMEM $end
+$var wire 1 ! clock $end
+$var wire 5 * MEMWBrt [4:0] $end
+$var wire 5 + MEMWBrd [4:0] $end
+$var wire 6 , MEMWBop [5:0] $end
+$var wire 5 - IDEXrt [4:0] $end
+$var wire 5 . IDEXrs [4:0] $end
+$var wire 6 / IDEXop [5:0] $end
+$var wire 5 0 EXMEMrd [4:0] $end
+$var wire 6 1 EXMEMop [5:0] $end
+$var wire 32 2 Ain [31:0] $end
+$var reg 32 3 EXMEMALUOut [31:0] $end
+$var reg 32 4 EXMEMB [31:0] $end
+$var reg 32 5 EXMEMIR [31:0] $end
+$var reg 32 6 IDEXA [31:0] $end
+$var reg 32 7 IDEXB [31:0] $end
+$var reg 32 8 IDEXIR [31:0] $end
+$var reg 32 9 IFIDIR [31:0] $end
+$var reg 32 : MEMWBIR [31:0] $end
+$var reg 32 ; MEMWBValue [31:0] $end
+$var reg 32 < PC [31:0] $end
+$var reg 6 = i [5:0] $end
+$var reg 11 > j [10:0] $end
+$var reg 11 ? k [10:0] $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+b10000000000 ?
+b10000000000 >
+b100000 =
+b0 <
+bx ;
+b100000 :
+b100000 9
+b100000 8
+bx 7
+bx 6
+b100000 5
+bx 4
+bx 3
+bx 2
+b0 1
+b0 0
+b0 /
+b0 .
+b0 -
+b0 ,
+b0 +
+b0 *
+0)
+0(
+0'
+0&
+0%
+0$
+bx #
+b0 "
+0!
+$end
+#5
+b0 2
+b0 #
+b0 7
+b0 6
+b100 <
+b10000010010100000100000 9
+b1 "
+1!
+#10
+0!
+#15
+b10 2
+b10 .
+b1 -
+b0 4
+b0 3
+b10000010010100000100000 8
+b1 #
+b1 7
+b10 6
+b1000 <
+b10001100101000110000000000000100 9
+b10 "
+1!
+#20
+0!
+#25
+1&
+b11 2
+b101 0
+b101 .
+b11 -
+b100011 /
+b0 ;
+b1 4
+b10000010010100000100000 5
+b11 3
+b10001100101000110000000000000100 8
+b11 #
+b11 7
+b101 6
+b1100 <
+b10101100101001110000000000000101 9
+b11 "
+1!
+#30
+0!
+#35
+0&
+b101 +
+b1 *
+b0 0
+b100011 1
+b101 2
+b111 -
+b101011 /
+b10000010010100000100000 :
+b11 ;
+b11 4
+b10001100101000110000000000000100 5
+b111 3
+b10101100101001110000000000000101 8
+b111 #
+b111 7
+b10000 <
+b11000000010000000100000 9
+b100 "
+1!
+#40
+0!
+#45
+1%
+b11111111111111111111111111111111 2
+b0 +
+b11 *
+b100011 ,
+b101011 1
+b11 .
+b0 -
+b0 /
+b10001100101000110000000000000100 :
+b11111111111111111111111111111111 ;
+b111 4
+b10101100101001110000000000000101 5
+b1010 3
+b11000000010000000100000 8
+b0 #
+b0 7
+b11 6
+b10100 <
+b1000010010011000000100000 9
+b101 "
+1!
+#50
+0!
+#55
+b1000 2
+0%
+b111 *
+b101011 ,
+b100 0
+b0 1
+b1000 .
+b1001 -
+b10101100101001110000000000000101 :
+b0 4
+b11000000010000000100000 5
+b11111111111111111111111111111111 3
+b1000010010011000000100000 8
+b1001 #
+b1001 7
+b1000 6
+b11000 <
+b10101100000001100000000000001100 9
+b110 "
+1!
+#60
+0!
+#65
+b0 2
+b100 +
+b0 *
+b0 ,
+b110 0
+b0 .
+b110 -
+b101011 /
+b11000000010000000100000 :
+b1001 4
+b1000010010011000000100000 5
+b10001 3
+b10101100000001100000000000001100 8
+b110 #
+b110 7
+b0 6
+b11100 <
+b110000000101000000100000 9
+b111 "
+1!
+#70
+0!
+#75
+b110 2
+b110 +
+b1001 *
+b0 0
+b101011 1
+b110 .
+b0 -
+b0 /
+b1000010010011000000100000 :
+b10001 ;
+b110 4
+b10101100000001100000000000001100 5
+b1100 3
+b110000000101000000100000 8
+b0 #
+b0 7
+b110 6
+b100000 <
+b10001100000010110000000000010000 9
+b1000 "
+1!
+#80
+0!
+#85
+b0 2
+b0 +
+b110 *
+b101011 ,
+b1010 0
+b0 1
+b0 .
+b1011 -
+b100011 /
+b10101100000001100000000000001100 :
+b0 4
+b110000000101000000100000 5
+b110 3
+b10001100000010110000000000010000 8
+b1011 #
+b1011 7
+b0 6
+b100100 <
+b100000 9
+b1001 "
+1!
+#90
+0!
+#95
+b1010 +
+b0 *
+b0 ,
+b0 0
+b100011 1
+b0 -
+b0 /
+b110000000101000000100000 :
+b110 ;
+b1011 4
+b10001100000010110000000000010000 5
+b10000 3
+b100000 8
+b0 #
+b0 7
+b101000 <
+b1010110110000000100000 9
+b1010 "
+1!
+#100
+0!
+#105
+b1 2
+b0 +
+b1011 *
+b100011 ,
+b0 1
+b1 .
+b1011 -
+b10001100000010110000000000010000 :
+b11111111111111111111111111111110 ;
+b0 4
+b100000 5
+b0 3
+b1010110110000000100000 8
+b1011 #
+b1011 7
+b1 6
+b101100 <
+b100000 9
+b1011 "
+1!
+#110
+0!
+#115
+b0 2
+b0 *
+b0 ,
+b1100 0
+b0 .
+b0 -
+b100000 :
+b0 ;
+b1011 4
+b1010110110000000100000 5
+b1100 3
+b100000 8
+b0 #
+b0 7
+b0 6
+b110000 <
+b1100 "
+1!
+#120
+0!
+#125
+b1100 +
+b1011 *
+b0 0
+b1010110110000000100000 :
+b1100 ;
+b0 4
+b100000 5
+b0 3
+b110100 <
+b1101 "
+1!
+#130
+0!
+#135
+b0 +
+b0 *
+b100000 :
+b0 ;
+b111000 <
+b1110 "
+1!
+#140
+0!
+#145
+b111100 <
+b1111 "
+1!
+#150
+0!
+#155
+b1000000 <
+b0 "
+1!
+#160
+0!