diff options
Diffstat (limited to 'ee4363/mp2/test_mipspipe.vcd')
| -rw-r--r-- | ee4363/mp2/test_mipspipe.vcd | 372 |
1 files changed, 372 insertions, 0 deletions
diff --git a/ee4363/mp2/test_mipspipe.vcd b/ee4363/mp2/test_mipspipe.vcd new file mode 100644 index 0000000..b75650b --- /dev/null +++ b/ee4363/mp2/test_mipspipe.vcd @@ -0,0 +1,372 @@ +$date + Thu Dec 17 11:20:12 2020 +$end +$version + Icarus Verilog +$end +$timescale + 1s +$end +$scope module test_mipspipe $end +$var reg 1 ! clock $end +$var reg 4 " clock_cycle [3:0] $end +$scope module u_mipspipe_mp2 $end +$var wire 32 # Bin [31:0] $end +$var wire 1 $ bypassAfromALUinWB $end +$var wire 1 % bypassAfromLWinWB $end +$var wire 1 & bypassAfromMEM $end +$var wire 1 ' bypassBfromALUinWB $end +$var wire 1 ( bypassBfromLWinWB $end +$var wire 1 ) bypassBfromMEM $end +$var wire 1 ! clock $end +$var wire 5 * MEMWBrt [4:0] $end +$var wire 5 + MEMWBrd [4:0] $end +$var wire 6 , MEMWBop [5:0] $end +$var wire 5 - IDEXrt [4:0] $end +$var wire 5 . IDEXrs [4:0] $end +$var wire 6 / IDEXop [5:0] $end +$var wire 5 0 EXMEMrd [4:0] $end +$var wire 6 1 EXMEMop [5:0] $end +$var wire 32 2 Ain [31:0] $end +$var reg 32 3 EXMEMALUOut [31:0] $end +$var reg 32 4 EXMEMB [31:0] $end +$var reg 32 5 EXMEMIR [31:0] $end +$var reg 32 6 IDEXA [31:0] $end +$var reg 32 7 IDEXB [31:0] $end +$var reg 32 8 IDEXIR [31:0] $end +$var reg 32 9 IFIDIR [31:0] $end +$var reg 32 : MEMWBIR [31:0] $end +$var reg 32 ; MEMWBValue [31:0] $end +$var reg 32 < PC [31:0] $end +$var reg 6 = i [5:0] $end +$var reg 11 > j [10:0] $end +$var reg 11 ? k [10:0] $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +b10000000000 ? +b10000000000 > +b100000 = +b0 < +bx ; +b100000 : +b100000 9 +b100000 8 +bx 7 +bx 6 +b100000 5 +bx 4 +bx 3 +bx 2 +b0 1 +b0 0 +b0 / +b0 . +b0 - +b0 , +b0 + +b0 * +0) +0( +0' +0& +0% +0$ +bx # +b0 " +0! +$end +#5 +b0 2 +b0 # +b0 7 +b0 6 +b100 < +b10000010010100000100000 9 +b1 " +1! +#10 +0! +#15 +b10 2 +b10 . +b1 - +b0 4 +b0 3 +b10000010010100000100000 8 +b1 # +b1 7 +b10 6 +b1000 < +b10001100101000110000000000000100 9 +b10 " +1! +#20 +0! +#25 +1& +b11 2 +b101 0 +b101 . +b11 - +b100011 / +b0 ; +b1 4 +b10000010010100000100000 5 +b11 3 +b10001100101000110000000000000100 8 +b11 # +b11 7 +b101 6 +b1100 < +b10101100101001110000000000000101 9 +b11 " +1! +#30 +0! +#35 +0& +b101 + +b1 * +b0 0 +b100011 1 +b101 2 +b111 - +b101011 / +b10000010010100000100000 : +b11 ; +b11 4 +b10001100101000110000000000000100 5 +b111 3 +b10101100101001110000000000000101 8 +b111 # +b111 7 +b10000 < +b11000000010000000100000 9 +b100 " +1! +#40 +0! +#45 +1% +b11111111111111111111111111111111 2 +b0 + +b11 * +b100011 , +b101011 1 +b11 . +b0 - +b0 / +b10001100101000110000000000000100 : +b11111111111111111111111111111111 ; +b111 4 +b10101100101001110000000000000101 5 +b1010 3 +b11000000010000000100000 8 +b0 # +b0 7 +b11 6 +b10100 < +b1000010010011000000100000 9 +b101 " +1! +#50 +0! +#55 +b1000 2 +0% +b111 * +b101011 , +b100 0 +b0 1 +b1000 . +b1001 - +b10101100101001110000000000000101 : +b0 4 +b11000000010000000100000 5 +b11111111111111111111111111111111 3 +b1000010010011000000100000 8 +b1001 # +b1001 7 +b1000 6 +b11000 < +b10101100000001100000000000001100 9 +b110 " +1! +#60 +0! +#65 +b0 2 +b100 + +b0 * +b0 , +b110 0 +b0 . +b110 - +b101011 / +b11000000010000000100000 : +b1001 4 +b1000010010011000000100000 5 +b10001 3 +b10101100000001100000000000001100 8 +b110 # +b110 7 +b0 6 +b11100 < +b110000000101000000100000 9 +b111 " +1! +#70 +0! +#75 +b110 2 +b110 + +b1001 * +b0 0 +b101011 1 +b110 . +b0 - +b0 / +b1000010010011000000100000 : +b10001 ; +b110 4 +b10101100000001100000000000001100 5 +b1100 3 +b110000000101000000100000 8 +b0 # +b0 7 +b110 6 +b100000 < +b10001100000010110000000000010000 9 +b1000 " +1! +#80 +0! +#85 +b0 2 +b0 + +b110 * +b101011 , +b1010 0 +b0 1 +b0 . +b1011 - +b100011 / +b10101100000001100000000000001100 : +b0 4 +b110000000101000000100000 5 +b110 3 +b10001100000010110000000000010000 8 +b1011 # +b1011 7 +b0 6 +b100100 < +b100000 9 +b1001 " +1! +#90 +0! +#95 +b1010 + +b0 * +b0 , +b0 0 +b100011 1 +b0 - +b0 / +b110000000101000000100000 : +b110 ; +b1011 4 +b10001100000010110000000000010000 5 +b10000 3 +b100000 8 +b0 # +b0 7 +b101000 < +b1010110110000000100000 9 +b1010 " +1! +#100 +0! +#105 +b1 2 +b0 + +b1011 * +b100011 , +b0 1 +b1 . +b1011 - +b10001100000010110000000000010000 : +b11111111111111111111111111111110 ; +b0 4 +b100000 5 +b0 3 +b1010110110000000100000 8 +b1011 # +b1011 7 +b1 6 +b101100 < +b100000 9 +b1011 " +1! +#110 +0! +#115 +b0 2 +b0 * +b0 , +b1100 0 +b0 . +b0 - +b100000 : +b0 ; +b1011 4 +b1010110110000000100000 5 +b1100 3 +b100000 8 +b0 # +b0 7 +b0 6 +b110000 < +b1100 " +1! +#120 +0! +#125 +b1100 + +b1011 * +b0 0 +b1010110110000000100000 : +b1100 ; +b0 4 +b100000 5 +b0 3 +b110100 < +b1101 " +1! +#130 +0! +#135 +b0 + +b0 * +b100000 : +b0 ; +b111000 < +b1110 " +1! +#140 +0! +#145 +b111100 < +b1111 " +1! +#150 +0! +#155 +b1000000 < +b0 " +1! +#160 +0! |