aaaaaaaaaaaaa

1 files changed, 372 insertions, 0 deletions

diff --git a/ee4363/mp2/test_mipspipe.vcd b/ee4363/mp2/test_mipspipe.vcd
new file mode 100644
index 0000000..b75650b
--- /dev/null
+++ b/ee4363/mp2/test_mipspipe.vcd
@@ -0,0 +1,372 @@
+$date
+	Thu Dec 17 11:20:12 2020
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module test_mipspipe $end
+$var reg 1 ! clock $end
+$var reg 4 " clock_cycle [3:0] $end
+$scope module u_mipspipe_mp2 $end
+$var wire 32 # Bin [31:0] $end
+$var wire 1 $ bypassAfromALUinWB $end
+$var wire 1 % bypassAfromLWinWB $end
+$var wire 1 & bypassAfromMEM $end
+$var wire 1 ' bypassBfromALUinWB $end
+$var wire 1 ( bypassBfromLWinWB $end
+$var wire 1 ) bypassBfromMEM $end
+$var wire 1 ! clock $end
+$var wire 5 * MEMWBrt [4:0] $end
+$var wire 5 + MEMWBrd [4:0] $end
+$var wire 6 , MEMWBop [5:0] $end
+$var wire 5 - IDEXrt [4:0] $end
+$var wire 5 . IDEXrs [4:0] $end
+$var wire 6 / IDEXop [5:0] $end
+$var wire 5 0 EXMEMrd [4:0] $end
+$var wire 6 1 EXMEMop [5:0] $end
+$var wire 32 2 Ain [31:0] $end
+$var reg 32 3 EXMEMALUOut [31:0] $end
+$var reg 32 4 EXMEMB [31:0] $end
+$var reg 32 5 EXMEMIR [31:0] $end
+$var reg 32 6 IDEXA [31:0] $end
+$var reg 32 7 IDEXB [31:0] $end
+$var reg 32 8 IDEXIR [31:0] $end
+$var reg 32 9 IFIDIR [31:0] $end
+$var reg 32 : MEMWBIR [31:0] $end
+$var reg 32 ; MEMWBValue [31:0] $end
+$var reg 32 < PC [31:0] $end
+$var reg 6 = i [5:0] $end
+$var reg 11 > j [10:0] $end
+$var reg 11 ? k [10:0] $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+b10000000000 ?
+b10000000000 >
+b100000 =
+b0 <
+bx ;
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+b100000 8
+bx 7
+bx 6
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+0)
+0(
+0'
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+0!
+$end
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